JP6293171B2 - 金属コンタクト開口を形成する方法 - Google Patents

金属コンタクト開口を形成する方法 Download PDF

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JP6293171B2
JP6293171B2 JP2015557170A JP2015557170A JP6293171B2 JP 6293171 B2 JP6293171 B2 JP 6293171B2 JP 2015557170 A JP2015557170 A JP 2015557170A JP 2015557170 A JP2015557170 A JP 2015557170A JP 6293171 B2 JP6293171 B2 JP 6293171B2
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Japan
Prior art keywords
hard mask
mask layer
layer
forming
photoresist
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Japanese (ja)
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JP2016510515A5 (enExample
JP2016510515A (ja
Inventor
ジェラルド ファーバー デビッド
ジェラルド ファーバー デビッド
リー トム
リー トム
ライトル スティーブ
ライトル スティーブ
Original Assignee
日本テキサス・インスツルメンツ株式会社
テキサス インスツルメンツ インコーポレイテッド
テキサス インスツルメンツ インコーポレイテッド
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2015557170A 2013-02-08 2014-02-10 金属コンタクト開口を形成する方法 Active JP6293171B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/762,529 2013-02-08
US13/762,529 US9054158B2 (en) 2013-02-08 2013-02-08 Method of forming a metal contact opening with a width that is smaller than the minimum feature size of a photolithographically-defined opening
PCT/US2014/015595 WO2014124376A1 (en) 2013-02-08 2014-02-10 Method of forming metal contact opening

Publications (3)

Publication Number Publication Date
JP2016510515A JP2016510515A (ja) 2016-04-07
JP2016510515A5 JP2016510515A5 (enExample) 2017-03-09
JP6293171B2 true JP6293171B2 (ja) 2018-03-14

Family

ID=51297723

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015557170A Active JP6293171B2 (ja) 2013-02-08 2014-02-10 金属コンタクト開口を形成する方法

Country Status (5)

Country Link
US (1) US9054158B2 (enExample)
EP (1) EP3033766B1 (enExample)
JP (1) JP6293171B2 (enExample)
CN (1) CN104956468B (enExample)
WO (1) WO2014124376A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9583609B2 (en) * 2013-03-25 2017-02-28 Texas Instruments Incorporated MOS transistor structure and method of forming the structure with vertically and horizontally-elongated metal contacts
CN108666263B (zh) * 2018-04-13 2020-06-16 上海华力集成电路制造有限公司 接触孔的制造方法
CN108470745A (zh) * 2018-04-28 2018-08-31 德淮半导体有限公司 图像传感器及其形成方法
US10867842B2 (en) * 2018-10-31 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for shrinking openings in forming integrated circuits
CN110690282B (zh) * 2019-08-23 2022-10-18 福建省福联集成电路有限公司 一种基于晶体管的电阻结构及其制作方法
DE102020113616A1 (de) * 2020-02-24 2021-08-26 Taiwan Semiconductor Manufacturing Co., Ltd. Hartmaskenschicht unter einer durchkontaktierungsstruktur in einer anzeigevorrichtung
US11682692B2 (en) 2020-02-24 2023-06-20 Taiwan Semiconductor Manufacturing Company, Ltd. Hard mask layer below via structure in display device

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3288884B2 (ja) * 1995-03-13 2002-06-04 株式会社東芝 レジストパターン形成方法
JP3305932B2 (ja) * 1995-09-19 2002-07-24 株式会社東芝 半導体装置およびその製造方法
JP4613364B2 (ja) * 2000-06-14 2011-01-19 学校法人東京電機大学 レジストパタン形成方法
US6570214B1 (en) * 2002-03-01 2003-05-27 Ching-Yuan Wu Scalable stack-gate flash memory cell and its contactless memory array
JP3585039B2 (ja) * 2002-03-25 2004-11-04 株式会社半導体先端テクノロジーズ ホール形成方法
JP3988592B2 (ja) * 2002-08-30 2007-10-10 ソニー株式会社 半導体装置の製造方法
JP3757213B2 (ja) * 2003-03-18 2006-03-22 富士通株式会社 半導体装置の製造方法
KR100540475B1 (ko) * 2003-04-04 2006-01-10 주식회사 하이닉스반도체 미세 패턴 형성이 가능한 반도체 장치 제조 방법
JP4278497B2 (ja) * 2003-11-26 2009-06-17 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
KR100819673B1 (ko) * 2006-12-22 2008-04-04 주식회사 하이닉스반도체 반도체 소자 및 그의 패턴 형성 방법
KR100827534B1 (ko) * 2006-12-28 2008-05-06 주식회사 하이닉스반도체 반도체 소자 및 그의 미세 패턴 형성 방법
JP2009238998A (ja) * 2008-03-27 2009-10-15 Epson Imaging Devices Corp コンタクトホールの形成方法、パターン形成方法、及び電気光学装置の製造方法
US20100099255A1 (en) * 2008-10-20 2010-04-22 Conley Willard E Method of forming a contact through an insulating layer
JP2010135624A (ja) * 2008-12-05 2010-06-17 Tokyo Electron Ltd 半導体装置の製造方法
US8252192B2 (en) * 2009-03-26 2012-08-28 Tokyo Electron Limited Method of pattern etching a dielectric film while removing a mask layer
KR101073075B1 (ko) * 2009-03-31 2011-10-12 주식회사 하이닉스반도체 이중 패터닝 공정을 이용한 반도체장치 제조 방법
US20120100717A1 (en) * 2010-10-26 2012-04-26 Texas Instruments Incorporated Trench lithography process
KR101671464B1 (ko) * 2010-12-02 2016-11-02 삼성전자주식회사 반도체 소자의 제조 방법
JP2012182474A (ja) * 2012-04-26 2012-09-20 Tokyo Electron Ltd 半導体装置の製造方法及び記憶媒体

Also Published As

Publication number Publication date
EP3033766A4 (en) 2017-08-09
WO2014124376A1 (en) 2014-08-14
EP3033766A1 (en) 2016-06-22
JP2016510515A (ja) 2016-04-07
EP3033766B1 (en) 2021-10-20
US20140227877A1 (en) 2014-08-14
CN104956468A (zh) 2015-09-30
US9054158B2 (en) 2015-06-09
CN104956468B (zh) 2017-09-08

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