JP6289621B2 - チョクラルスキ法で成長したインゴットからスライスされた高ドープシリコンウエハ中の酸素析出 - Google Patents

チョクラルスキ法で成長したインゴットからスライスされた高ドープシリコンウエハ中の酸素析出 Download PDF

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JP6289621B2
JP6289621B2 JP2016519519A JP2016519519A JP6289621B2 JP 6289621 B2 JP6289621 B2 JP 6289621B2 JP 2016519519 A JP2016519519 A JP 2016519519A JP 2016519519 A JP2016519519 A JP 2016519519A JP 6289621 B2 JP6289621 B2 JP 6289621B2
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single crystal
crystal silicon
concentration
silicon wafer
type single
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JP2016526783A5 (https=
JP2016526783A (ja
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ロバート・ジェイ・フォルスター
ウラジミール・ブイ・ボロンコフ
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SunEdison Semiconductor Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/60—Impurity distributions or concentrations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3822—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/12—Diffusion of dopants within, into or out of semiconductor bodies or layers between a solid phase and a gaseous phase
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H10P36/20—Intrinsic gettering, i.e. thermally inducing defects by using oxygen present in the silicon body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering

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  • Crystals, And After-Treatments Of Crystals (AREA)
JP2016519519A 2013-06-11 2014-05-23 チョクラルスキ法で成長したインゴットからスライスされた高ドープシリコンウエハ中の酸素析出 Active JP6289621B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/914,925 US9634098B2 (en) 2013-06-11 2013-06-11 Oxygen precipitation in heavily doped silicon wafers sliced from ingots grown by the Czochralski method
US13/914,925 2013-06-11
PCT/US2014/039363 WO2014200686A1 (en) 2013-06-11 2014-05-23 Oxygen precipitation in heavily doped silicon wafers sliced from ingots grown by the czochralski method

Publications (3)

Publication Number Publication Date
JP2016526783A JP2016526783A (ja) 2016-09-05
JP2016526783A5 JP2016526783A5 (https=) 2017-07-20
JP6289621B2 true JP6289621B2 (ja) 2018-03-07

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JP2016519519A Active JP6289621B2 (ja) 2013-06-11 2014-05-23 チョクラルスキ法で成長したインゴットからスライスされた高ドープシリコンウエハ中の酸素析出

Country Status (5)

Country Link
US (1) US9634098B2 (https=)
JP (1) JP6289621B2 (https=)
KR (3) KR102071304B1 (https=)
DE (2) DE112014002781B9 (https=)
WO (1) WO2014200686A1 (https=)

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Publication number Publication date
KR102071304B1 (ko) 2020-01-31
DE112014002781B4 (de) 2020-06-18
WO2014200686A1 (en) 2014-12-18
US20140361408A1 (en) 2014-12-11
DE112014007334B3 (de) 2023-08-24
KR20160019495A (ko) 2016-02-19
KR102172905B1 (ko) 2020-11-03
US9634098B2 (en) 2017-04-25
DE112014002781B9 (de) 2021-07-29
KR20200044152A (ko) 2020-04-28
JP2016526783A (ja) 2016-09-05
KR20200011563A (ko) 2020-02-03
KR102172904B1 (ko) 2020-11-03
DE112014002781T5 (de) 2016-03-10

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