JP6264852B2 - タイミング調整回路および半導体集積回路装置 - Google Patents

タイミング調整回路および半導体集積回路装置 Download PDF

Info

Publication number
JP6264852B2
JP6264852B2 JP2013235911A JP2013235911A JP6264852B2 JP 6264852 B2 JP6264852 B2 JP 6264852B2 JP 2013235911 A JP2013235911 A JP 2013235911A JP 2013235911 A JP2013235911 A JP 2013235911A JP 6264852 B2 JP6264852 B2 JP 6264852B2
Authority
JP
Japan
Prior art keywords
circuit
voltage
clock
control voltage
timing adjustment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2013235911A
Other languages
English (en)
Japanese (ja)
Other versions
JP2015095860A (ja
JP2015095860A5 (enExample
Inventor
松田　篤
篤 松田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Socionext Inc
Original Assignee
Socionext Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Socionext Inc filed Critical Socionext Inc
Priority to JP2013235911A priority Critical patent/JP6264852B2/ja
Priority to US14/508,739 priority patent/US9172385B2/en
Priority to CN201410602548.3A priority patent/CN104639157B/zh
Publication of JP2015095860A publication Critical patent/JP2015095860A/ja
Publication of JP2015095860A5 publication Critical patent/JP2015095860A5/ja
Application granted granted Critical
Publication of JP6264852B2 publication Critical patent/JP6264852B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal

Landscapes

  • Pulse Circuits (AREA)
  • Dram (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Logic Circuits (AREA)
JP2013235911A 2013-11-14 2013-11-14 タイミング調整回路および半導体集積回路装置 Active JP6264852B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2013235911A JP6264852B2 (ja) 2013-11-14 2013-11-14 タイミング調整回路および半導体集積回路装置
US14/508,739 US9172385B2 (en) 2013-11-14 2014-10-07 Timing adjustment circuit and semiconductor integrated circuit device
CN201410602548.3A CN104639157B (zh) 2013-11-14 2014-10-31 定时调整电路和半导体集成电路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013235911A JP6264852B2 (ja) 2013-11-14 2013-11-14 タイミング調整回路および半導体集積回路装置

Publications (3)

Publication Number Publication Date
JP2015095860A JP2015095860A (ja) 2015-05-18
JP2015095860A5 JP2015095860A5 (enExample) 2016-06-16
JP6264852B2 true JP6264852B2 (ja) 2018-01-24

Family

ID=53043284

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013235911A Active JP6264852B2 (ja) 2013-11-14 2013-11-14 タイミング調整回路および半導体集積回路装置

Country Status (3)

Country Link
US (1) US9172385B2 (enExample)
JP (1) JP6264852B2 (enExample)
CN (1) CN104639157B (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9543937B2 (en) * 2014-09-03 2017-01-10 Microsoft Technology Licensing, Llc Multi-phase clock generation
US9438255B1 (en) * 2015-07-31 2016-09-06 Inphi Corporation High frequency delay lock loop systems
US10615805B2 (en) 2017-02-03 2020-04-07 Microsoft Technology Licensing, Llc Output driver pulse overlap control
JP2020128947A (ja) * 2019-02-12 2020-08-27 ソニーセミコンダクタソリューションズ株式会社 検出器
US11206026B2 (en) 2019-09-06 2021-12-21 SK Hynix Inc. Delay line, a delay locked loop circuit and a semiconductor apparatus using the delay line and the delay locked loop circuit
US11750201B2 (en) 2019-09-06 2023-09-05 SK Hynix Inc. Delay line, a delay locked loop circuit and a semiconductor apparatus using the delay line and the delay locked loop circuit
KR102804159B1 (ko) * 2019-12-24 2025-05-09 에스케이하이닉스 주식회사 반도체 장치 및 이의 테스트 방법
CN113810029B (zh) * 2020-06-12 2025-01-03 圣邦微电子（北京）股份有限公司 一种检测数据相关性的电路
KR20220104490A (ko) * 2021-01-18 2022-07-26 에스케이하이닉스 주식회사 클럭 생성 회로 및 이를 포함하는 전압 생성 회로

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5497126A (en) * 1993-11-09 1996-03-05 Motorola, Inc. Phase synchronization circuit and method therefor for a phase locked loop
JP3179382B2 (ja) * 1997-08-27 2001-06-25 山形日本電気株式会社 Ｐｌｌ回路
NL1021440C2 (nl) * 2001-09-28 2004-07-15 Samsung Electronics Co Ltd Vertragingsvergrendelde lus met meervoudige fasen.
JP3993860B2 (ja) * 2004-04-19 2007-10-17 富士通株式会社 Ｄｌｌ回路
JP2006025131A (ja) 2004-07-07 2006-01-26 Renesas Technology Corp Ｐｌｌ回路およびｄｌｌ回路
US7034591B2 (en) * 2004-08-30 2006-04-25 Texas Instruments Incorporated False-lock-free delay locked loop circuit and method
JP4036868B2 (ja) * 2005-03-31 2008-01-23 日本テキサス・インスツルメンツ株式会社 遅延同期ループ回路
TWI299944B (en) * 2005-12-08 2008-08-11 Novatek Microelectronics Corp Delay locked loop circuit and method
US7936221B2 (en) * 2006-09-15 2011-05-03 Texas Instruments Incorporated Computation spreading for spur reduction in a digital phase lock loop
KR100818181B1 (ko) * 2007-09-20 2008-03-31 주식회사 아나패스 데이터 구동 회로 및 지연 고정 루프 회로
CN101183872B (zh) * 2007-11-01 2011-07-27 钰创科技股份有限公司 全频率宽度的多重相位延迟锁定回路
JP5242320B2 (ja) * 2008-09-29 2013-07-24 富士通テン株式会社 発振回路、及び映像表示装置
KR101027678B1 (ko) 2008-11-10 2011-04-12 주식회사 하이닉스반도체 Ｄｌｌ 회로 및 그 제어 방법
US7791420B2 (en) * 2008-12-09 2010-09-07 Taiwan Semiconductor Manufacturing Company, Ltd. Phase-locked loop with start-up circuit
JP5588254B2 (ja) * 2009-08-04 2014-09-10 キヤノン株式会社 遅延同期ループ回路
US8339165B2 (en) * 2009-12-07 2012-12-25 Qualcomm Incorporated Configurable digital-analog phase locked loop
US9112507B2 (en) * 2010-03-09 2015-08-18 Taiwan Semiconductor Manufacturing Co., Ltd. Phase-locked loop start up circuit
US8248124B2 (en) * 2010-06-03 2012-08-21 Intel Corporation Methods and apparatuses for delay-locked loops and phase-locked loops
US8354866B2 (en) * 2010-11-25 2013-01-15 Freescale Semiconductor, Inc. PLL start-up circuit
US9008254B2 (en) * 2013-08-30 2015-04-14 Realtek Semiconductor Corp. Method and apparatus for suppressing a deterministic clock jitter

Also Published As

Publication number Publication date
US20150130520A1 (en) 2015-05-14
JP2015095860A (ja) 2015-05-18
CN104639157B (zh) 2018-07-06
CN104639157A (zh) 2015-05-20
US9172385B2 (en) 2015-10-27

Similar Documents

Publication Publication Date Title
JP6264852B2 (ja) タイミング調整回路および半導体集積回路装置
CN104113303B (zh) 50%占空比时钟产生电路
US8232844B2 (en) Synchronous oscillator, clock recovery apparatus, clock distribution circuit, and multi-mode injection circuit
CN102361453B (zh) 用于锁相环的高速占空比调节和双端转单端电路
JP5588254B2 (ja) 遅延同期ループ回路
US7663515B2 (en) High-speed serial interface circuit and electronic instrument
US7668277B2 (en) Apparatus and method for clock data recovery with low lock frequency
JP2001160752A (ja) 位相同期ループの同期方法、位相同期ループ及び該位相同期ループを備えた半導体装置
US6856558B1 (en) Integrated circuit devices having high precision digital delay lines therein
US7482841B1 (en) Differential bang-bang phase detector (BBPD) with latency reduction
CN113315510A (zh) 时钟生成电路和使用时钟生成电路的半导体装置
CN101521499A (zh) 相位检测器、相位比较器、以及时钟同步设备
US20140286470A1 (en) Phase locked loop and clock and data recovery circuit
KR100861919B1 (ko) 다 위상 신호 발생기 및 그 방법
TWI791914B (zh) 分頻器電路、用於分頻器電路的方法及補償電路
JP2009044579A (ja) クロック生成回路及び電子機器
JP5035119B2 (ja) リタイミング回路及び分周システム
JPWO2004079907A1 (ja) 位相比較回路およびｃｄｒ回路
JP5257122B2 (ja) クロック生成回路
US9780797B2 (en) CMOS interpolator for a serializer/deserializer communication application
JP5286414B2 (ja) 半導体記憶回路
JP6512835B2 (ja) Ｄｌｌ回路及びディスプレイドライバ
KR100685604B1 (ko) 지터 성분이 감소된 내부 클럭 신호를 발생하는 ｄｌｌ
KR20100079123A (ko) 아날로그 지연 동기 루프 회로
Yang et al. A low power 120-to-520Mb/s clock and data recovery circuit for PWM signaling scheme

Legal Events

Date Code Title Description
A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20150612

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160426

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20160426

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20170309

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20170516

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170629

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20171128

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20171211

R150 Certificate of patent or registration of utility model

Ref document number: 6264852

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150