JP6238712B2 - 薄膜トランジスタ基板およびその製造方法 - Google Patents

薄膜トランジスタ基板およびその製造方法 Download PDF

Info

Publication number
JP6238712B2
JP6238712B2 JP2013251616A JP2013251616A JP6238712B2 JP 6238712 B2 JP6238712 B2 JP 6238712B2 JP 2013251616 A JP2013251616 A JP 2013251616A JP 2013251616 A JP2013251616 A JP 2013251616A JP 6238712 B2 JP6238712 B2 JP 6238712B2
Authority
JP
Japan
Prior art keywords
gate
film
electrode
insulating film
contact hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2013251616A
Other languages
English (en)
Japanese (ja)
Other versions
JP2015108732A (ja
JP2015108732A5 (enExample
Inventor
恭佑 樋渡
恭佑 樋渡
井上　和式
和式 井上
耕治 小田
耕治 小田
展昭 石賀
展昭 石賀
顕祐 長山
顕祐 長山
津村　直樹
直樹 津村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2013251616A priority Critical patent/JP6238712B2/ja
Priority to US14/552,860 priority patent/US9508750B2/en
Publication of JP2015108732A publication Critical patent/JP2015108732A/ja
Publication of JP2015108732A5 publication Critical patent/JP2015108732A5/ja
Application granted granted Critical
Publication of JP6238712B2 publication Critical patent/JP6238712B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/18, H10D48/04 and H10D48/07, with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/469—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
    • H01L21/47—Organic layers, e.g. photoresist
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Landscapes

  • Engineering & Computer Science (AREA)
  • Liquid Crystal (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2013251616A 2013-12-05 2013-12-05 薄膜トランジスタ基板およびその製造方法 Active JP6238712B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2013251616A JP6238712B2 (ja) 2013-12-05 2013-12-05 薄膜トランジスタ基板およびその製造方法
US14/552,860 US9508750B2 (en) 2013-12-05 2014-11-25 Thin film transistor substrate and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013251616A JP6238712B2 (ja) 2013-12-05 2013-12-05 薄膜トランジスタ基板およびその製造方法

Publications (3)

Publication Number Publication Date
JP2015108732A JP2015108732A (ja) 2015-06-11
JP2015108732A5 JP2015108732A5 (enExample) 2017-01-05
JP6238712B2 true JP6238712B2 (ja) 2017-11-29

Family

ID=53271976

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013251616A Active JP6238712B2 (ja) 2013-12-05 2013-12-05 薄膜トランジスタ基板およびその製造方法

Country Status (2)

Country Link
US (1) US9508750B2 (enExample)
JP (1) JP6238712B2 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6278633B2 (ja) * 2013-07-26 2018-02-14 三菱電機株式会社 薄膜トランジスタアレイ基板およびその製造方法、並びに、液晶表示装置およびその製造方法
JP6315966B2 (ja) * 2013-12-11 2018-04-25 三菱電機株式会社 アクティブマトリックス基板およびその製造方法
WO2016021319A1 (ja) * 2014-08-07 2016-02-11 シャープ株式会社 アクティブマトリクス基板、液晶パネル、および、アクティブマトリクス基板の製造方法
CN105140234B (zh) * 2015-07-28 2018-03-27 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
CN108027541B (zh) * 2015-09-11 2020-12-15 三菱电机株式会社 薄膜晶体管基板及其制造方法
US10243010B2 (en) * 2015-11-30 2019-03-26 Sharp Kabushiki Kaisha Semiconductor substrate and display device
WO2017159601A1 (ja) * 2016-03-14 2017-09-21 シャープ株式会社 表示装置
JP6689108B2 (ja) 2016-03-22 2020-04-28 三菱電機株式会社 薄膜トランジスタ基板およびその製造方法
CN109313371B (zh) * 2016-06-09 2021-09-14 夏普株式会社 显示装置及其制造方法
CN106252217B (zh) * 2016-08-25 2019-05-24 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板和显示装置
CN107623042A (zh) * 2017-09-21 2018-01-23 深圳市华星光电半导体显示技术有限公司 薄膜晶体管结构及其制作方法
JP2019169660A (ja) * 2018-03-26 2019-10-03 三菱電機株式会社 薄膜トランジスタ基板、表示装置、および、薄膜トランジスタ基板の製造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3829881A (en) * 1969-09-18 1974-08-13 Matsushita Electric Industrial Co Ltd Variable capacitance device
JPH04206775A (ja) * 1990-11-30 1992-07-28 Casio Comput Co Ltd 薄膜トランジスタ
WO2003040441A1 (fr) 2001-11-05 2003-05-15 Japan Science And Technology Agency Film mince monocristallin homologue a super-reseau naturel, procede de preparation et dispositif dans lequel est utilise ledit film mince monocristallin
JP4164562B2 (ja) 2002-09-11 2008-10-15 独立行政法人科学技術振興機構 ホモロガス薄膜を活性層として用いる透明薄膜電界効果型トランジスタ
JP2003330388A (ja) * 2002-05-15 2003-11-19 Semiconductor Energy Lab Co Ltd 半導体装置及びその作製方法
JP5006598B2 (ja) 2005-09-16 2012-08-22 キヤノン株式会社 電界効果型トランジスタ
JP4645488B2 (ja) * 2006-03-15 2011-03-09 ソニー株式会社 液晶装置及び電子機器
JP4466708B2 (ja) * 2007-03-15 2010-05-26 エプソンイメージングデバイス株式会社 液晶装置
JP5079463B2 (ja) 2007-11-20 2012-11-21 株式会社ジャパンディスプレイウェスト 液晶表示装置及びその製造方法
JP4442684B2 (ja) 2007-11-29 2010-03-31 エプソンイメージングデバイス株式会社 液晶表示装置及びその製造方法
JP2009151285A (ja) 2007-11-30 2009-07-09 Epson Imaging Devices Corp 液晶表示装置及びその製造方法
KR20090060756A (ko) * 2007-12-10 2009-06-15 삼성전자주식회사 표시 패널 및 이의 제조방법
JP2010039394A (ja) * 2008-08-07 2010-02-18 Hitachi Displays Ltd 表示装置及び表示装置の製造方法
KR20130015829A (ko) * 2011-08-05 2013-02-14 삼성디스플레이 주식회사 표시 기판, 표시 기판의 제조 방법 및 표시 기판을 포함하는 액정 표시 장치

Also Published As

Publication number Publication date
JP2015108732A (ja) 2015-06-11
US9508750B2 (en) 2016-11-29
US20150162351A1 (en) 2015-06-11

Similar Documents

Publication Publication Date Title
JP6238712B2 (ja) 薄膜トランジスタ基板およびその製造方法
JP6230253B2 (ja) Ｔｆｔアレイ基板およびその製造方法
JP5275519B2 (ja) 表示装置用基板及びその製造方法、表示装置
US9461077B2 (en) Active matrix substrate and method for manufacturing the same
CN108027541B (zh) 薄膜晶体管基板及其制造方法
TW201321872A (zh) 邊緣電場切換型液晶顯示裝置用陣列基板及其製造方法
JP6436660B2 (ja) 薄膜トランジスタ基板およびその製造方法
CN107112367B (zh) 薄膜晶体管基板、薄膜晶体管基板的制造方法、液晶显示装置
WO2015098183A1 (ja) アクティブマトリクス基板の製造方法および表示装置の製造方法ならびに表示装置
CN102466934A (zh) 高透光率面内切换模式液晶显示设备及其制造方法
JP2015108732A5 (enExample)
JP2012018970A (ja) 薄膜トランジスタアレイ基板、その製造方法、及び液晶表示装置
WO2012117695A1 (ja) 半導体装置及びその製造方法並びに表示装置
JP6501514B2 (ja) 薄膜トランジスタ基板およびその製造方法
JP2014232824A (ja) 薄膜トランジスタ、表示パネル用基板、表示パネル、表示装置および薄膜トランジスタの製造方法
WO2011142061A1 (ja) 薄膜トランジスタ基板及びそれを備えた液晶表示装置
US9690154B2 (en) Liquid crystal display panel and method of manufacturing the same
WO2011161875A1 (ja) 表示装置用基板及びその製造方法、表示装置
KR101399214B1 (ko) 액정 표시 장치 및 그 제조 방법
JP6584157B2 (ja) 薄膜トランジスタ、薄膜トランジスタ基板、液晶表示装置及び薄膜トランジスタの製造方法
JP6478819B2 (ja) 薄膜トランジスタ基板およびその製造方法
JP6482256B2 (ja) 薄膜トランジスタ基板および液晶表示装置
KR101962917B1 (ko) 액정 디스플레이 장치와 이의 제조방법
US20230367166A1 (en) Method of manufacturing active matrix substrate and liquid crystal display device

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20161121

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20161121

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20170801

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20170731

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170828

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20171003

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20171031

R150 Certificate of patent or registration of utility model

Ref document number: 6238712

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250