JP6140616B2 - ダブルパターニングされるリソグラフィプロセスのためのパターン分割分解ストラテジー - Google Patents

ダブルパターニングされるリソグラフィプロセスのためのパターン分割分解ストラテジー Download PDF

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JP6140616B2
JP6140616B2 JP2013556909A JP2013556909A JP6140616B2 JP 6140616 B2 JP6140616 B2 JP 6140616B2 JP 2013556909 A JP2013556909 A JP 2013556909A JP 2013556909 A JP2013556909 A JP 2013556909A JP 6140616 B2 JP6140616 B2 JP 6140616B2
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Japan
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pattern
interconnect
parallel
root
tracks
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Japanese (ja)
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JP2014509785A5 (https=
JP2014509785A (ja
Inventor
ウォルター ブラッチフォード ジェームズ
ウォルター ブラッチフォード ジェームズ
Original Assignee
日本テキサス・インスツルメンツ株式会社
テキサス インスツルメンツ インコーポレイテッド
テキサス インスツルメンツ インコーポレイテッド
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Priority claimed from US13/410,188 external-priority patent/US8575020B2/en
Application filed by 日本テキサス・インスツルメンツ株式会社, テキサス インスツルメンツ インコーポレイテッド, テキサス インスツルメンツ インコーポレイテッド filed Critical 日本テキサス・インスツルメンツ株式会社
Publication of JP2014509785A publication Critical patent/JP2014509785A/ja
Publication of JP2014509785A5 publication Critical patent/JP2014509785A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H10W20/0633—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material using subtractive patterning of the conductive members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof

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  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
JP2013556909A 2011-03-02 2012-03-02 ダブルパターニングされるリソグラフィプロセスのためのパターン分割分解ストラテジー Active JP6140616B2 (ja)

Applications Claiming Priority (11)

Application Number Priority Date Filing Date Title
US201161448437P 2011-03-02 2011-03-02
US201161448451P 2011-03-02 2011-03-02
US201161448423P 2011-03-02 2011-03-02
US201161448447P 2011-03-02 2011-03-02
US61/448,423 2011-03-02
US61/448,451 2011-03-02
US61/448,447 2011-03-02
US61/448,437 2011-03-02
US13/410,188 US8575020B2 (en) 2011-03-02 2012-03-01 Pattern-split decomposition strategy for double-patterned lithography process
US13/410,188 2012-03-01
PCT/US2012/027534 WO2012119098A2 (en) 2011-03-02 2012-03-02 Pattern-split decomposition strategy for double-patterned lithography process

Publications (3)

Publication Number Publication Date
JP2014509785A JP2014509785A (ja) 2014-04-21
JP2014509785A5 JP2014509785A5 (https=) 2015-04-16
JP6140616B2 true JP6140616B2 (ja) 2017-05-31

Family

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Family Applications (2)

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JP2013556909A Active JP6140616B2 (ja) 2011-03-02 2012-03-02 ダブルパターニングされるリソグラフィプロセスのためのパターン分割分解ストラテジー
JP2013556653A Active JP6134652B2 (ja) 2011-03-02 2012-03-02 ハイブリッドピッチ分割パターン分割リソグラフィプロセス

Family Applications After (1)

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JP2013556653A Active JP6134652B2 (ja) 2011-03-02 2012-03-02 ハイブリッドピッチ分割パターン分割リソグラフィプロセス

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Country Link
JP (2) JP6140616B2 (https=)
WO (2) WO2012119098A2 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9583609B2 (en) * 2013-03-25 2017-02-28 Texas Instruments Incorporated MOS transistor structure and method of forming the structure with vertically and horizontally-elongated metal contacts
CN109983564B (zh) * 2016-11-16 2023-05-02 东京毅力科创株式会社 亚分辨率衬底图案化的方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5561317A (en) * 1990-08-24 1996-10-01 Canon Kabushiki Kaisha Method of manufacturing semiconductor devices
JP3050210B2 (ja) * 1998-09-24 2000-06-12 株式会社ニコン 露光方泡および該方法を用いる素子製造方法
JP4109944B2 (ja) * 2002-09-20 2008-07-02 キヤノン株式会社 固体撮像装置の製造方法
SG126877A1 (en) * 2005-04-12 2006-11-29 Asml Masktools Bv A method, program product and apparatus for performing double exposure lithography
US7824842B2 (en) * 2005-10-05 2010-11-02 Asml Netherlands B.V. Method of patterning a positive tone resist layer overlaying a lithographic substrate
EP1843202B1 (en) * 2006-04-06 2015-02-18 ASML Netherlands B.V. Method for performing dark field double dipole lithography
JP2007294500A (ja) * 2006-04-21 2007-11-08 Nec Electronics Corp 半導体装置およびその製造方法
KR100861363B1 (ko) * 2006-07-21 2008-10-01 주식회사 하이닉스반도체 이중 노광을 위한 패턴분할 방법
JP2006303541A (ja) * 2006-07-28 2006-11-02 Renesas Technology Corp 半導体集積回路装置の製造方法
JP4945367B2 (ja) * 2006-08-14 2012-06-06 エーエスエムエル マスクツールズ ビー．ブイ． 回路パターンを複数の回路パターンに分離する装置および方法
JP2008071838A (ja) * 2006-09-12 2008-03-27 Nec Electronics Corp 半導体装置の製造方法
JP5032948B2 (ja) * 2006-11-14 2012-09-26 エーエスエムエル マスクツールズ ビー．ブイ． Ｄｐｔプロセスで用いられるパターン分解を行うための方法、プログラムおよび装置
JP2008311502A (ja) * 2007-06-15 2008-12-25 Toshiba Corp パターン形成方法
JP5218227B2 (ja) * 2008-12-12 2013-06-26 信越化学工業株式会社 パターン形成方法
KR101532012B1 (ko) * 2008-12-24 2015-06-30 삼성전자주식회사 반도체 소자 및 반도체 소자의 패턴 형성 방법
JP5235719B2 (ja) * 2009-02-27 2013-07-10 株式会社日立ハイテクノロジーズ パターン測定装置

Also Published As

Publication number Publication date
WO2012119098A3 (en) 2012-11-08
JP6134652B2 (ja) 2017-05-24
JP2014509785A (ja) 2014-04-21
WO2012119105A3 (en) 2012-11-15
JP2014510403A (ja) 2014-04-24
WO2012119105A2 (en) 2012-09-07
WO2012119098A2 (en) 2012-09-07

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