WO2012119105A2 - Hybrid pitch-split pattern-split litrography process - Google Patents

Hybrid pitch-split pattern-split litrography process Download PDF

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Publication number
WO2012119105A2
WO2012119105A2 PCT/US2012/027554 US2012027554W WO2012119105A2 WO 2012119105 A2 WO2012119105 A2 WO 2012119105A2 US 2012027554 W US2012027554 W US 2012027554W WO 2012119105 A2 WO2012119105 A2 WO 2012119105A2
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WO
WIPO (PCT)
Prior art keywords
interconnect
pattern
route
parallel
exposed areas
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PCT/US2012/027554
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French (fr)
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WO2012119105A3 (en
Inventor
James Walter Blatchford
Original Assignee
Texas Instruments Incorporated
Texas Instruments Japan Limited
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Priority claimed from US13/410,145 external-priority patent/US8372743B2/en
Application filed by Texas Instruments Incorporated, Texas Instruments Japan Limited filed Critical Texas Instruments Incorporated
Priority to JP2013556653A priority Critical patent/JP6134652B2/en
Publication of WO2012119105A2 publication Critical patent/WO2012119105A2/en
Publication of WO2012119105A3 publication Critical patent/WO2012119105A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This relates to the field of integrated circuits and, more particularly, to photolithography processes for forming integrated circuits.
  • Integrated circuits may be formed using photolithography processes with illuminations sources having wavelengths more than twice a desired pitch of metal interconnect lines in the integrated circuits. Attaining desired tradeoffs between fabrication costs and fabrication yield may be difficult. For example, technology nodes at and beyond the 28 nanometer node using 193 nanometer illumination sources may require more than one pattern step to obtain desired first metal interconnect layouts. Forming crossovers between adjacent parallel route tracks and separated lines in the first metal level with desired lateral dimensions may be problematic.
  • An integrated circuit may be formed by a process of forming a first interconnect pattern in a plurality of parallel route tracks, forming a second interconnect pattern in the plurality of parallel route tracks, and forming a third interconnect pattern in the plurality of parallel route tracks.
  • the three interconnect patterns are formed using photolithography processes which have illumination sources capable of resolving features with a pitch distance in a direction perpendicular to the route tracks substantially equal to twice a pitch distance of the parallel route tracks.
  • the first interconnect pattern includes a first lead pattern which extends to a first point in a first instance of the parallel route tracks.
  • the second interconnect pattern includes a second lead pattern which is parallel to and immediately adjacent to the first lead pattern in an immediately adjacent instance of the parallel route tracks.
  • the third interconnect pattern includes a third lead pattern which is parallel to and immediately adjacent to the second pattern in an immediately adjacent instance of the parallel route tracks and which extends to a second point in the first instance of the parallel route tracks, such that the second point is laterally separated from the first point by a distance less than one and one-half times a space between adjacent instances of the interconnect patterns in the parallel route tracks.
  • a metal interconnect formation process is performed which forms metal interconnect lines in an interconnect level defined by the first interconnect pattern, the second interconnect pattern and the third interconnect pattern.
  • a first lead of the metal interconnect lines is formed in the first lead pattern and extends to the first point.
  • a second lead of the metal interconnect lines is formed in the second lead pattern.
  • a third lead of the metal interconnect lines is formed in the third lead pattern and extends to the second point.
  • FIGS. 1A - 1C depict example illumination sources for photolithographic processes which may be used to form integrated circuits according to embodiments described herein.
  • FIGS. 2A - 2G are top views of an integrated circuit formed according a first embodiment using a damascene metal process and an illumination source with a dipole component, depicted in successive stages of fabrication.
  • FIGS. 3A - 3C depict example illumination sources for photolithographic processes which may be used to form integrated circuits according to embodiments described herein.
  • FIG. 4 is a top view of an integrated circuit formed according the process described in reference to FIG. 2A through FIG. 2G using an isotropic illumination source, for example any of the illuminations sources described in reference to FIG. 3A through FIG. 3C.
  • An integrated circuit may be formed by a process of forming a first interconnect pattern in a plurality of parallel route tracks, forming a second interconnect pattern in the plurality of parallel route tracks, and forming a third interconnect pattern in the plurality of parallel route tracks.
  • the three interconnect patterns are formed using photolithography processes which have illumination sources capable of resolving features with a pitch distance in a direction perpendicular to the route tracks equal to twice a pitch distance of the parallel route tracks.
  • the first interconnect pattern includes a first lead pattern which extends to a first point in a first instance of the parallel route tracks.
  • the second interconnect pattern includes a second lead pattern which is parallel to and immediately adjacent to the first lead pattern in an immediately adjacent instance of the parallel route tracks.
  • the third interconnect pattern includes a third lead pattern which is parallel to and immediately adjacent to the second pattern in an immediately adjacent instance of the parallel route tracks and which extends to a second point in the first instance of the parallel route tracks, such that the second point is laterally separated from the first point by a distance less than one and one-half times a space between adjacent instances of the interconnect patterns in the parallel route tracks.
  • a metal interconnect formation process is performed which forms metal interconnect lines in an interconnect level defined by the first interconnect pattern and the second interconnect pattern.
  • a first lead of the metal interconnect lines is formed in the first lead pattern and extends to the first point.
  • a second lead of the metal interconnect lines is formed in the second lead pattern.
  • a third lead of the metal interconnect lines is formed in the third lead pattern and extends to the second point.
  • FIGS. 1A - 1C depict example illumination sources for photolithographic processes which may be used to form integrated circuits according to embodiments described herein.
  • FIG. 1 A depicts an off-axis illumination source with a moderate dipole component; the emitting area is configured in two large dipole regions 100 along the vertical direction and smaller source regions 102 along the horizontal and diagonal directions.
  • FIG. IB depicts an off-axis illumination source with a strong dipole component; the emitting area is configured in two large dipole regions 104 along the vertical direction and smaller, weaker source regions 106 along the horizontal and diagonal directions.
  • FIG. 1C depicts an off-axis illumination source with a dipole component; the emitting area is configured in two dipole regions 108 along the vertical direction and a distributed annular region 110.
  • FIGS. 2A - 2G are top views of an integrated circuit formed according a first embodiment using a damascene metal process and an illumination source with a dipole component, depicted in successive stages of fabrication.
  • the instant embodiment uses an illumination source with a dipole component, for example any of the illuminations sources described in reference to FIG. 1A through FIG. 1C.
  • the integrated circuit 200 is formed in and on a semiconductor substrate 202, which may be, for example, a single crystal silicon wafer, a silicon wafer with silicon- germanium regions, a silicon-on-insulator (SOI) wafer, a hybrid orientation technology (HOT) wafer with regions of different crystal orientations, or other material appropriate for fabrication of the integrated circuit 200.
  • SOI silicon-on-insulator
  • HET hybrid orientation technology
  • a dielectric layer 204 is formed over the substrate 202.
  • the dielectric layer 204 may be a stack of dielectric sub-layers, and may include, for example a pre- metal dielectric (PMD) layer and an inter-level dielectric (ILD) layer.
  • the PMD layer may include a PMD liner, a PMD main layer, and an optional PMD cap layer, not shown.
  • the PMD liner may include silicon nitride or silicon dioxide, 10 to 100 nanometers thick, deposited by plasma enhanced chemical vapor deposition (PECVD) on an existing top surface of the integrated circuit 200.
  • PECVD plasma enhanced chemical vapor deposition
  • the PMD main layer may be a layer of silicon dioxide formed by a high aspect ration process (HARP) followed by a layer of silicon dioxide, phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG), commonly 100 to 1000 nanometers thick, deposited by a PECVD process on a top surface of the PMD liner, and sometimes leveled by a chemical-mechanical polish (CMP) process.
  • the optional PMD cap layer is commonly 10 to 100 nanometers of a hard material such as silicon nitride, silicon carbide nitride or silicon carbide, formed on a top surface of the PMD main layer.
  • the ILD layer may include, for example, an etch stop layer of 5 to 25 nanometers of silicon nitride, silicon carbide, or silicon carbide nitride, a main layer of 100 to 200 nanometers of low-k dielectric material such as organosilicate glass (OSG), carbon-doped silicon oxides (SiCO or CDO) or dielectric material formed from methylsilsesquioxane (MSQ), or possibly ultra low-k dielectric material such as porous OSG (p-OSG), and a cap layer of 10 to 40 nanometers of silicon nitride, silicon carbide nitride or silicon carbide.
  • OSG organosilicate glass
  • SiCO carbon-doped silicon oxides
  • MSQ methylsilsesquioxane
  • p-OSG porous OSG
  • a first interconnect pattern 208 depicted in FIG. 2A with a stipple pattern, is formed of photoresist over the dielectric layer 204 which creates a first plurality of exposed areas 210 in the parallel route tracks 206.
  • a photolithography process used to form the first interconnect pattern 208 is capable of forming lead patterns in the parallel route tracks 206 with a pitch distance in a direction perpendicular to the route tracks 206 substantially equal to twice a pitch distance of the parallel route tracks 206, so that an instance of the first plurality of exposed areas 210 in an instance of the parallel route tracks 206 is free of instances of the first plurality of exposed areas 210 immediately adjacent to the exposed areas 210 instance in an immediately adjacent instance of the parallel route tracks 206.
  • the first plurality of exposed areas 210 includes instances of first lead patterns 212 in instances of the of parallel route tracks 206.
  • the first lead patterns 212 extend to instances of a first point 214 in instances of the parallel route tracks 206.
  • the first lead patterns 212 may terminate at the first point 214 or may branch at the first point 214 to another instance of the parallel route tracks 206.
  • the first interconnect pattern 208 may be formed of an amplified photoresist suitable for 193 nanometer radiation, and developed using a positive tone develop process such as exposure to an alkaline aqueous developing solution. In another version, the first interconnect pattern 208 may be formed of photoresist and developed using a negative tone develop process. In one version of the instant embodiment, the illumination source may provide 193 nanometer radiation, and the pitch distance of the parallel route tracks 206 may be 40 to 42 nanometers.
  • a first interconnect trench etch process is performed which removes dielectric material from the dielectric layer 204 in the first plurality of exposed areas 210 to form a first plurality of interconnect trenches 216.
  • the first plurality of interconnect trenches 216 includes instances of first lead trenches 218, formed in areas defined by the first lead patterns 212, which extend to the instances of the first point 214.
  • the first interconnect pattern 208 is removed after the first interconnect trench etch process is completed, for example by exposing the integrated circuit 200 to an oxygen containing plasma, followed by a wet cleanup to remove any organic residue from the top surface of the dielectric layer 204.
  • FIG. 2C a second interconnect pattern 220, depicted in FIG.
  • the second plurality of exposed areas 222 includes instances of second lead patterns 224 which are parallel to and immediately adjacent to the instances of the first lead patterns 212, and hence to the instances of the first lead trenches 218, in immediately adjacent instances of the parallel route tracks 206.
  • a second interconnect trench etch process is performed which removes dielectric material from the dielectric layer 204 in the second plurality of exposed areas 222 to form a second plurality of interconnect trenches 226, including a second plurality of second lead trenches 228 in areas defined by the second lead patterns 224.
  • the second lead trenches 228 are parallel to and immediately adjacent to the instances of the first lead trenches 218 in immediately adjacent instances of the parallel route tracks 206.
  • the second interconnect pattern 220 is removed after the second interconnect trench etch process is completed, for example as described in reference to FIG. 2B.
  • a third interconnect pattern 230 is formed of photoresist over the dielectric layer 204 which creates a third plurality of exposed areas 232 in the parallel route tracks 206.
  • a photolithography process used to form the third interconnect pattern 230 has similar resolution characteristics as the photolithography process used to form the first interconnect pattern 208 , so that an instance of the third plurality of exposed areas 232 in an instance of the parallel route tracks 206 is free of instances of the third plurality of exposed areas 232 immediately adjacent to the exposed areas 232 instance in an immediately adjacent instance of the parallel route tracks 206.
  • the third plurality of exposed areas 232 includes instances of third lead patterns 234 which are parallel to and immediately adjacent to the instances of the second lead pattern 224, and hence to the instances of the second lead trenches 228, in an immediately adjacent instance of the parallel route tracks 206 and which extend to instances of a second point 236 proximate to the instances of the first point 214 in the same instances of the route tracks containing the instances of the first point 214, such that the instances of the second point 236 are laterally separated from corresponding instances of the first point 214 by a distance less than one and one -half times a space between adjacent instances of the interconnect patterns in the parallel route tracks 206.
  • the instances of the second point 236 may be laterally separated from corresponding instances of the first point 214 by a distance less than the space between adjacent instances of the interconnect patterns in the parallel route tracks 206.
  • a third interconnect trench etch process is performed which removes dielectric material from the dielectric layer 204 in the third plurality of exposed areas 232 to form a third plurality of interconnect trenches 238, including a third plurality of third lead trenches 240 in areas defined by the third lead patterns 234.
  • the third lead trenches 240 are parallel to and immediately adjacent to the instances of the second lead trenches 228 in an immediately adjacent instance of the parallel route tracks 206 and extend to instances of the second point 236 proximate to the instances of the first point 214 in the same instances of the route tracks containing the instances of the first point 214.
  • the third interconnect pattern 230 is removed after the third interconnect trench etch process is completed, for example as described in reference to FIG. 2B. It will be recognized that the three interconnect patterns 208, 220 and 230 and corresponding interconnect trench etch processes may be performed in any order so as to provide the configuration of interconnect trenches depicted in FIG. 2F.
  • a damascene metal interconnect formation process is performed which forms metal interconnect lines 242 in the first plurality of interconnect trenches 216, the second plurality of interconnect trenches 226 and the third plurality of interconnect trenches 238.
  • the metal interconnect lines 242 are depicted in FIG. 2E with a star hatch pattern.
  • the damascene metal interconnect formation process may include, for example, forming a tantalum nitride liner 1 to 5 nanometers thick in the first plurality of interconnect trenches 216, the second plurality of interconnect trenches 226 and the third plurality of interconnect trenches 238 by an atomic layer deposition (ALD) process, forming a copper seed layer 5 to 80 nanometers thick on the liner by sputtering, electroplating copper on the seed layer so as to fill the first plurality of interconnect trenches 216, the second plurality of interconnect trenches 226 and the third plurality of interconnect trenches 238, and subsequently removing copper and liner metal from a top surface of the dielectric layer 204 by a copper CMP process.
  • ALD atomic layer deposition
  • the metal interconnect lines 242 include a plurality of first leads 244 formed in the first lead trenches 218, a plurality of second leads 246 formed in the second lead trenches 228 and a plurality of third leads 248 formed in the third lead trenches 240.
  • the first leads 244 extend to the instances of the first point 214 in instances of the parallel route tracks 206.
  • the second leads 246 are parallel to and immediately adjacent to the instances of the first leads 244 in immediately adjacent instances of the parallel route tracks 206.
  • the third leads 248 are parallel to and immediately adjacent to the instances of the second leads 246 in an immediately adjacent instance of the parallel route tracks 206 and extend to the instances of the second point 236 proximate to the instances of the first point 214 in the same instances of the route tracks containing the instances of the first point 214.
  • Crossover segments 250 may have a minimum width parallel to the route tracks 206 that is greater than twice the width of the metal interconnect lines 242 in the route tracks 206 because of the dipole configuration of the illumination sources used to form the interconnect patterns 208, 220 and 230.
  • the crossover segments 250 may, for example, extend to two adjacent instances of the parallel route tracks 206, or may extend to two instances of the parallel route tracks which are separated by another instance of the parallel route tracks 206.
  • Forming the metal interconnect lines 242 using the three interconnect patterns and three interconnect trench etch processes as described in reference to FIG. 2A through FIG. 2G may desirably provide configuration of the metal interconnect lines 242 in less space on the integrated circuit 200 than other configurations of the metal interconnect lines 242 formed by two interconnect patterns and two interconnect trench etch processes. Forming the metal interconnect lines 242 in less space may advantageously provide a lower cost of the integrated circuit 200.
  • FIG. 3A through FIG. 3C depict example illumination sources for photolithographic processes which may be used to form integrated circuits according to embodiments described herein.
  • FIG. 3A depicts an isotropic off-axis illumination source, in which the emitting area 300 has an annular configuration.
  • FIG. 3B depicts a quadruple off-axis illumination source, in which the emitting area 302 is configured in four regions uniformly spaced around an optical axis of the illumination source so as to provide substantially equal spatial resolution in both horizontal and vertical directions.
  • FIG. 3A depicts an isotropic off-axis illumination source, in which the emitting area 300 has an annular configuration.
  • FIG. 3B depicts a quadruple off-axis illumination source, in which the emitting area 302 is configured in four regions uniformly spaced around an optical axis of the illumination source so as to provide substantially equal spatial resolution in both horizontal and vertical directions.
  • 3C depicts a composite dipole-quadrupole-octopole off-axis illumination source, in which the emitting area is configured in two strong emitting regions 304 along the vertical direction, two moderate emitting regions 306 along the horizontal direction, and four weak emitting regions 308 along diagonal directions.
  • FIG. 4 is a top view of an integrated circuit formed according the process described in reference to FIGS. 2 A - 2G using an isotropic illumination source, for example any of the illuminations sources described in reference to FIG. 3A through FIG. 3C.
  • the integrated circuit 400 is formed in and on a semiconductor substrate 402 with a dielectric layer 404 is formed over the substrate 402 as described in reference to FIG. 2A. Areas for a plurality of parallel route tracks 406 are defined over the integrated circuit 400.
  • Metal interconnect lines 408 are formed in the dielectric layer 404 using three photolithographic processes and three interconnect trench etch process followed by a damascene metal interconnect formation process, as described in reference to FIG. 2A through FIG. 2G.
  • the metal interconnect lines 408 are depicted in FIG. 4 with a star hatch pattern.
  • the metal interconnect lines 408 include a plurality of first leads 410 defined by a first interconnect pattern, a plurality of second leads 412 defined by a second interconnect pattern, and a plurality of third leads 414 defined by a third interconnect pattern.
  • the first leads 410 extend to the instances of a first point 416 in instances of the parallel route tracks 406.
  • the second leads 412 are parallel to and immediately adjacent to the instances of the first leads 410 in immediately adjacent instances of the parallel route tracks 406.
  • the third leads 414 are parallel to and immediately adjacent to the instances of the second leads 412 in an immediately adjacent instance of the parallel route tracks 406 and extend to the instances of a second point 418 proximate to the instances of the first point 416 in the same instances of the route tracks containing the instances of the first point 416, such that the instances of the second point 418 are laterally separated from corresponding instances of the first point 416 by a distance less than one and one -half times a space between adjacent metal interconnect lines 408 in the parallel route tracks 406.
  • Crossover segments 420 may have a minimum width parallel to the route tracks 406 that is less than one and one-half times a width of the metal interconnect lines 408 in the route tracks 406 because of the isotropic configuration of the illumination sources used to form the interconnect patterns.
  • Forming the metal interconnect lines 408 using the three interconnect patterns and three interconnect trench etch processes as described in reference to FIGS. 2 A - 2G with isotropic illumination sources may desirably provide configuration of the metal interconnect lines 408 in less space on the integrated circuit 400 than other configurations of the metal interconnect lines 408 formed by two interconnect patterns and two interconnect trench etch processes. Forming the metal interconnect lines 408 in less space may advantageously provide a lower cost of the integrated circuit 400.

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Abstract

An integrated circuit may be formed by a process of forming a three interconnect patterns in a plurality of parallel route tracks (206), using photolithography processes which have illumination sources capable of a pitch distance twice the pitch distance of the parallel route tracks (206). The first interconnect pattern (208) includes a first lead pattern (212) which extends to a first point. The second interconnect pattern (220) includes a second lead pattern (224) which is parallel to and immediately adjacent to the first lead pattern (212). The third interconnect pattern (23) includes a third lead pattern (234) which is parallel to and immediately adjacent to the second lead pattern (224) and which extends to a second point (236) in the first instance of the parallel route tracks, laterally separated from the first point (214) by a distance less than one and one-half times a space between adjacent patterns in the parallel route tracks.

Description

HYBRID PITCH-SPLIT PATTERN-SPLIT LITHOGRAPHY PROCESS
[0001] This relates to the field of integrated circuits and, more particularly, to photolithography processes for forming integrated circuits.
BACKGROUND
[0002] Integrated circuits may be formed using photolithography processes with illuminations sources having wavelengths more than twice a desired pitch of metal interconnect lines in the integrated circuits. Attaining desired tradeoffs between fabrication costs and fabrication yield may be difficult. For example, technology nodes at and beyond the 28 nanometer node using 193 nanometer illumination sources may require more than one pattern step to obtain desired first metal interconnect layouts. Forming crossovers between adjacent parallel route tracks and separated lines in the first metal level with desired lateral dimensions may be problematic.
SUMMARY
[0003] An integrated circuit may be formed by a process of forming a first interconnect pattern in a plurality of parallel route tracks, forming a second interconnect pattern in the plurality of parallel route tracks, and forming a third interconnect pattern in the plurality of parallel route tracks. The three interconnect patterns are formed using photolithography processes which have illumination sources capable of resolving features with a pitch distance in a direction perpendicular to the route tracks substantially equal to twice a pitch distance of the parallel route tracks. The first interconnect pattern includes a first lead pattern which extends to a first point in a first instance of the parallel route tracks. The second interconnect pattern includes a second lead pattern which is parallel to and immediately adjacent to the first lead pattern in an immediately adjacent instance of the parallel route tracks. The third interconnect pattern includes a third lead pattern which is parallel to and immediately adjacent to the second pattern in an immediately adjacent instance of the parallel route tracks and which extends to a second point in the first instance of the parallel route tracks, such that the second point is laterally separated from the first point by a distance less than one and one-half times a space between adjacent instances of the interconnect patterns in the parallel route tracks. A metal interconnect formation process is performed which forms metal interconnect lines in an interconnect level defined by the first interconnect pattern, the second interconnect pattern and the third interconnect pattern. A first lead of the metal interconnect lines is formed in the first lead pattern and extends to the first point. A second lead of the metal interconnect lines is formed in the second lead pattern. A third lead of the metal interconnect lines is formed in the third lead pattern and extends to the second point. BRIEF DESCRIPTION OF THE DRAWINGS
[0004] FIGS. 1A - 1C depict example illumination sources for photolithographic processes which may be used to form integrated circuits according to embodiments described herein.
[0005] FIGS. 2A - 2G are top views of an integrated circuit formed according a first embodiment using a damascene metal process and an illumination source with a dipole component, depicted in successive stages of fabrication.
[0006] FIGS. 3A - 3C depict example illumination sources for photolithographic processes which may be used to form integrated circuits according to embodiments described herein.
[0007] FIG. 4 is a top view of an integrated circuit formed according the process described in reference to FIG. 2A through FIG. 2G using an isotropic illumination source, for example any of the illuminations sources described in reference to FIG. 3A through FIG. 3C.
DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
[0008] An integrated circuit may be formed by a process of forming a first interconnect pattern in a plurality of parallel route tracks, forming a second interconnect pattern in the plurality of parallel route tracks, and forming a third interconnect pattern in the plurality of parallel route tracks. The three interconnect patterns are formed using photolithography processes which have illumination sources capable of resolving features with a pitch distance in a direction perpendicular to the route tracks equal to twice a pitch distance of the parallel route tracks. The first interconnect pattern includes a first lead pattern which extends to a first point in a first instance of the parallel route tracks. The second interconnect pattern includes a second lead pattern which is parallel to and immediately adjacent to the first lead pattern in an immediately adjacent instance of the parallel route tracks. The third interconnect pattern includes a third lead pattern which is parallel to and immediately adjacent to the second pattern in an immediately adjacent instance of the parallel route tracks and which extends to a second point in the first instance of the parallel route tracks, such that the second point is laterally separated from the first point by a distance less than one and one-half times a space between adjacent instances of the interconnect patterns in the parallel route tracks. A metal interconnect formation process is performed which forms metal interconnect lines in an interconnect level defined by the first interconnect pattern and the second interconnect pattern. A first lead of the metal interconnect lines is formed in the first lead pattern and extends to the first point. A second lead of the metal interconnect lines is formed in the second lead pattern. A third lead of the metal interconnect lines is formed in the third lead pattern and extends to the second point.
[0009] FIGS. 1A - 1C depict example illumination sources for photolithographic processes which may be used to form integrated circuits according to embodiments described herein. FIG. 1 A depicts an off-axis illumination source with a moderate dipole component; the emitting area is configured in two large dipole regions 100 along the vertical direction and smaller source regions 102 along the horizontal and diagonal directions. FIG. IB depicts an off-axis illumination source with a strong dipole component; the emitting area is configured in two large dipole regions 104 along the vertical direction and smaller, weaker source regions 106 along the horizontal and diagonal directions. FIG. 1C depicts an off-axis illumination source with a dipole component; the emitting area is configured in two dipole regions 108 along the vertical direction and a distributed annular region 110.
[0010] FIGS. 2A - 2G are top views of an integrated circuit formed according a first embodiment using a damascene metal process and an illumination source with a dipole component, depicted in successive stages of fabrication. The instant embodiment uses an illumination source with a dipole component, for example any of the illuminations sources described in reference to FIG. 1A through FIG. 1C. Referring to FIG. 2A, the integrated circuit 200 is formed in and on a semiconductor substrate 202, which may be, for example, a single crystal silicon wafer, a silicon wafer with silicon- germanium regions, a silicon-on-insulator (SOI) wafer, a hybrid orientation technology (HOT) wafer with regions of different crystal orientations, or other material appropriate for fabrication of the integrated circuit 200.
[0011] A dielectric layer 204 is formed over the substrate 202. The dielectric layer 204 may be a stack of dielectric sub-layers, and may include, for example a pre- metal dielectric (PMD) layer and an inter-level dielectric (ILD) layer. The PMD layer may include a PMD liner, a PMD main layer, and an optional PMD cap layer, not shown. The PMD liner may include silicon nitride or silicon dioxide, 10 to 100 nanometers thick, deposited by plasma enhanced chemical vapor deposition (PECVD) on an existing top surface of the integrated circuit 200. The PMD main layer may be a layer of silicon dioxide formed by a high aspect ration process (HARP) followed by a layer of silicon dioxide, phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG), commonly 100 to 1000 nanometers thick, deposited by a PECVD process on a top surface of the PMD liner, and sometimes leveled by a chemical-mechanical polish (CMP) process. The optional PMD cap layer is commonly 10 to 100 nanometers of a hard material such as silicon nitride, silicon carbide nitride or silicon carbide, formed on a top surface of the PMD main layer.
[0012] The ILD layer may include, for example, an etch stop layer of 5 to 25 nanometers of silicon nitride, silicon carbide, or silicon carbide nitride, a main layer of 100 to 200 nanometers of low-k dielectric material such as organosilicate glass (OSG), carbon-doped silicon oxides (SiCO or CDO) or dielectric material formed from methylsilsesquioxane (MSQ), or possibly ultra low-k dielectric material such as porous OSG (p-OSG), and a cap layer of 10 to 40 nanometers of silicon nitride, silicon carbide nitride or silicon carbide.
[0013] Areas for a plurality of parallel route tracks 206 are defined over the integrated circuit 200. A first interconnect pattern 208, depicted in FIG. 2A with a stipple pattern, is formed of photoresist over the dielectric layer 204 which creates a first plurality of exposed areas 210 in the parallel route tracks 206. A photolithography process used to form the first interconnect pattern 208 is capable of forming lead patterns in the parallel route tracks 206 with a pitch distance in a direction perpendicular to the route tracks 206 substantially equal to twice a pitch distance of the parallel route tracks 206, so that an instance of the first plurality of exposed areas 210 in an instance of the parallel route tracks 206 is free of instances of the first plurality of exposed areas 210 immediately adjacent to the exposed areas 210 instance in an immediately adjacent instance of the parallel route tracks 206.
[0014] The first plurality of exposed areas 210 includes instances of first lead patterns 212 in instances of the of parallel route tracks 206. The first lead patterns 212 extend to instances of a first point 214 in instances of the parallel route tracks 206. The first lead patterns 212, for example, may terminate at the first point 214 or may branch at the first point 214 to another instance of the parallel route tracks 206.
[0015] In one version of the instant embodiment, the first interconnect pattern 208 may be formed of an amplified photoresist suitable for 193 nanometer radiation, and developed using a positive tone develop process such as exposure to an alkaline aqueous developing solution. In another version, the first interconnect pattern 208 may be formed of photoresist and developed using a negative tone develop process. In one version of the instant embodiment, the illumination source may provide 193 nanometer radiation, and the pitch distance of the parallel route tracks 206 may be 40 to 42 nanometers.
[0016] Referring to FIG. 2B, a first interconnect trench etch process is performed which removes dielectric material from the dielectric layer 204 in the first plurality of exposed areas 210 to form a first plurality of interconnect trenches 216. The first plurality of interconnect trenches 216 includes instances of first lead trenches 218, formed in areas defined by the first lead patterns 212, which extend to the instances of the first point 214. The first interconnect pattern 208 is removed after the first interconnect trench etch process is completed, for example by exposing the integrated circuit 200 to an oxygen containing plasma, followed by a wet cleanup to remove any organic residue from the top surface of the dielectric layer 204.
[0017] Referring to FIG. 2C, a second interconnect pattern 220, depicted in FIG.
2C with a stipple pattern, is formed of photoresist over the dielectric layer 204 which creates a second plurality of exposed areas 222 in the parallel route tracks 206. A photolithography process used to form the second interconnect pattern 220 has similar resolution characteristics as the photolithography process used to form the first interconnect pattern 208 , so that an instance of the second plurality of exposed areas 222 in an instance of the parallel route tracks 206 is free of instances of the second plurality of exposed areas 222 immediately adjacent to the exposed areas 222 instance in an immediately adjacent instance of the parallel route tracks 206. The second plurality of exposed areas 222 includes instances of second lead patterns 224 which are parallel to and immediately adjacent to the instances of the first lead patterns 212, and hence to the instances of the first lead trenches 218, in immediately adjacent instances of the parallel route tracks 206.
[0018] Referring to FIG. 2D, a second interconnect trench etch process is performed which removes dielectric material from the dielectric layer 204 in the second plurality of exposed areas 222 to form a second plurality of interconnect trenches 226, including a second plurality of second lead trenches 228 in areas defined by the second lead patterns 224. The second lead trenches 228 are parallel to and immediately adjacent to the instances of the first lead trenches 218 in immediately adjacent instances of the parallel route tracks 206. The second interconnect pattern 220 is removed after the second interconnect trench etch process is completed, for example as described in reference to FIG. 2B.
[0019] Referring to FIG. 2E, a third interconnect pattern 230, depicted in FIG. 2C with a stipple pattern, is formed of photoresist over the dielectric layer 204 which creates a third plurality of exposed areas 232 in the parallel route tracks 206. A photolithography process used to form the third interconnect pattern 230 has similar resolution characteristics as the photolithography process used to form the first interconnect pattern 208 , so that an instance of the third plurality of exposed areas 232 in an instance of the parallel route tracks 206 is free of instances of the third plurality of exposed areas 232 immediately adjacent to the exposed areas 232 instance in an immediately adjacent instance of the parallel route tracks 206. The third plurality of exposed areas 232 includes instances of third lead patterns 234 which are parallel to and immediately adjacent to the instances of the second lead pattern 224, and hence to the instances of the second lead trenches 228, in an immediately adjacent instance of the parallel route tracks 206 and which extend to instances of a second point 236 proximate to the instances of the first point 214 in the same instances of the route tracks containing the instances of the first point 214, such that the instances of the second point 236 are laterally separated from corresponding instances of the first point 214 by a distance less than one and one -half times a space between adjacent instances of the interconnect patterns in the parallel route tracks 206. In one version of the instant embodiment, the instances of the second point 236 may be laterally separated from corresponding instances of the first point 214 by a distance less than the space between adjacent instances of the interconnect patterns in the parallel route tracks 206.
[0020] Referring to FIG. 2F, a third interconnect trench etch process is performed which removes dielectric material from the dielectric layer 204 in the third plurality of exposed areas 232 to form a third plurality of interconnect trenches 238, including a third plurality of third lead trenches 240 in areas defined by the third lead patterns 234. The third lead trenches 240 are parallel to and immediately adjacent to the instances of the second lead trenches 228 in an immediately adjacent instance of the parallel route tracks 206 and extend to instances of the second point 236 proximate to the instances of the first point 214 in the same instances of the route tracks containing the instances of the first point 214. The third interconnect pattern 230 is removed after the third interconnect trench etch process is completed, for example as described in reference to FIG. 2B. It will be recognized that the three interconnect patterns 208, 220 and 230 and corresponding interconnect trench etch processes may be performed in any order so as to provide the configuration of interconnect trenches depicted in FIG. 2F.
[0021] Referring to FIG. 2G, a damascene metal interconnect formation process is performed which forms metal interconnect lines 242 in the first plurality of interconnect trenches 216, the second plurality of interconnect trenches 226 and the third plurality of interconnect trenches 238. The metal interconnect lines 242 are depicted in FIG. 2E with a star hatch pattern. The damascene metal interconnect formation process may include, for example, forming a tantalum nitride liner 1 to 5 nanometers thick in the first plurality of interconnect trenches 216, the second plurality of interconnect trenches 226 and the third plurality of interconnect trenches 238 by an atomic layer deposition (ALD) process, forming a copper seed layer 5 to 80 nanometers thick on the liner by sputtering, electroplating copper on the seed layer so as to fill the first plurality of interconnect trenches 216, the second plurality of interconnect trenches 226 and the third plurality of interconnect trenches 238, and subsequently removing copper and liner metal from a top surface of the dielectric layer 204 by a copper CMP process.
[0022] The metal interconnect lines 242 include a plurality of first leads 244 formed in the first lead trenches 218, a plurality of second leads 246 formed in the second lead trenches 228 and a plurality of third leads 248 formed in the third lead trenches 240. The first leads 244 extend to the instances of the first point 214 in instances of the parallel route tracks 206. The second leads 246 are parallel to and immediately adjacent to the instances of the first leads 244 in immediately adjacent instances of the parallel route tracks 206. The third leads 248 are parallel to and immediately adjacent to the instances of the second leads 246 in an immediately adjacent instance of the parallel route tracks 206 and extend to the instances of the second point 236 proximate to the instances of the first point 214 in the same instances of the route tracks containing the instances of the first point 214.
[0023] Crossover segments 250 may have a minimum width parallel to the route tracks 206 that is greater than twice the width of the metal interconnect lines 242 in the route tracks 206 because of the dipole configuration of the illumination sources used to form the interconnect patterns 208, 220 and 230. The crossover segments 250 may, for example, extend to two adjacent instances of the parallel route tracks 206, or may extend to two instances of the parallel route tracks which are separated by another instance of the parallel route tracks 206.
[0024] Forming the metal interconnect lines 242 using the three interconnect patterns and three interconnect trench etch processes as described in reference to FIG. 2A through FIG. 2G may desirably provide configuration of the metal interconnect lines 242 in less space on the integrated circuit 200 than other configurations of the metal interconnect lines 242 formed by two interconnect patterns and two interconnect trench etch processes. Forming the metal interconnect lines 242 in less space may advantageously provide a lower cost of the integrated circuit 200.
[0025] FIG. 3A through FIG. 3C depict example illumination sources for photolithographic processes which may be used to form integrated circuits according to embodiments described herein. FIG. 3A depicts an isotropic off-axis illumination source, in which the emitting area 300 has an annular configuration. FIG. 3B depicts a quadruple off-axis illumination source, in which the emitting area 302 is configured in four regions uniformly spaced around an optical axis of the illumination source so as to provide substantially equal spatial resolution in both horizontal and vertical directions. FIG. 3C depicts a composite dipole-quadrupole-octopole off-axis illumination source, in which the emitting area is configured in two strong emitting regions 304 along the vertical direction, two moderate emitting regions 306 along the horizontal direction, and four weak emitting regions 308 along diagonal directions.
[0026] FIG. 4 is a top view of an integrated circuit formed according the process described in reference to FIGS. 2 A - 2G using an isotropic illumination source, for example any of the illuminations sources described in reference to FIG. 3A through FIG. 3C. Referring to FIG. 4, the integrated circuit 400 is formed in and on a semiconductor substrate 402 with a dielectric layer 404 is formed over the substrate 402 as described in reference to FIG. 2A. Areas for a plurality of parallel route tracks 406 are defined over the integrated circuit 400.
[0027] Metal interconnect lines 408 are formed in the dielectric layer 404 using three photolithographic processes and three interconnect trench etch process followed by a damascene metal interconnect formation process, as described in reference to FIG. 2A through FIG. 2G. The metal interconnect lines 408 are depicted in FIG. 4 with a star hatch pattern. The metal interconnect lines 408 include a plurality of first leads 410 defined by a first interconnect pattern, a plurality of second leads 412 defined by a second interconnect pattern, and a plurality of third leads 414 defined by a third interconnect pattern. The first leads 410 extend to the instances of a first point 416 in instances of the parallel route tracks 406. The second leads 412 are parallel to and immediately adjacent to the instances of the first leads 410 in immediately adjacent instances of the parallel route tracks 406. The third leads 414 are parallel to and immediately adjacent to the instances of the second leads 412 in an immediately adjacent instance of the parallel route tracks 406 and extend to the instances of a second point 418 proximate to the instances of the first point 416 in the same instances of the route tracks containing the instances of the first point 416, such that the instances of the second point 418 are laterally separated from corresponding instances of the first point 416 by a distance less than one and one -half times a space between adjacent metal interconnect lines 408 in the parallel route tracks 406.
[0028] Crossover segments 420 may have a minimum width parallel to the route tracks 406 that is less than one and one-half times a width of the metal interconnect lines 408 in the route tracks 406 because of the isotropic configuration of the illumination sources used to form the interconnect patterns. Forming the metal interconnect lines 408 using the three interconnect patterns and three interconnect trench etch processes as described in reference to FIGS. 2 A - 2G with isotropic illumination sources may desirably provide configuration of the metal interconnect lines 408 in less space on the integrated circuit 400 than other configurations of the metal interconnect lines 408 formed by two interconnect patterns and two interconnect trench etch processes. Forming the metal interconnect lines 408 in less space may advantageously provide a lower cost of the integrated circuit 400.
[0029] Those skilled in the art will appreciate that modifications may be made to the described example embodiments, and also that many other embodiments are possible, within the scope of the claimed invention.

Claims

CLAIMS What is claimed is:
1. A process of forming an integrated circuit, comprising the steps of:
forming a dielectric layer over a substrate;
defining a plurality of parallel route tracks having a pitch distance in said dielectric layer;
forming a first interconnect pattern in said plurality of parallel route tracks including a first lead pattern located in a first route track of said plurality of parallel route tracks;
forming a second interconnect pattern in said plurality of parallel route tracks including a second lead pattern located in a second route track of said plurality of parallel route tracks immediately adjacent to said first route track;
forming a third interconnect pattern in said plurality of parallel route tracks including a third lead pattern located in said first route track, wherein said third lead pattern is separated from said first lead pattern in the first route track by a distance less than one and one-half times a space between said first lead pattern and said second lead pattern;
wherein said first interconnect pattern, said second interconnect pattern and said third interconnect pattern are formed using three distinct photolithography processes which have a dipole illumination source capable of resolving patterns in alternate instances of said plurality of parallel route tracks and not capable of resolving patterns in immediately adjacent instances of said plurality of parallel route tracks; and
forming metal interconnect lines in said dielectric layer as defined by said first interconnect pattern, said second interconnect pattern and said third interconnect pattern.
2. The process of claim 1, in which said dipole illumination source provides 193 nanometer radiation; and said pitch distance of said plurality of parallel route tracks is 40 to 42 nanometers.
3. The process of claim 1, wherein said first lead pattern terminates at a point in the first route track that is at said distance from said third lead pattern.
4. The process of claim 1, wherein said first lead pattern branches to form a crossover at a point in the first route track that is at said distance from said third lead pattern.
5. The process of claim 4, wherein said crossover extends to a third route track on an opposite side of said second route track from said first route track.
6. The process of claim 4, in which said crossover has a minimum width parallel to said first route track that is greater than said pitch distance.
7. The process of claim 4, in which said crossover has a minimum width parallel to said first route track that is less than two-thirds of said pitch distance.
8. A process of forming an integrated circuit, comprising the steps of:
forming a dielectric layer over a substrate;
defining a plurality of parallel route tracks in said dielectric layer including a first route track, a second route track and a third route track, wherein said second route track is immediately adjacent said first route track and said third route track, said plurality of parallel route tracks having a pitch distance;
forming a first interconnect pattern creating a plurality of first exposed areas including a first lead pattern, wherein said first lead pattern is located in a first portion of said second route track;
performing a first trench etch process to form a plurality of first interconnect trenches in said plurality of first exposed areas;
forming a second interconnect pattern creating a plurality of second exposed areas including a second lead pattern, wherein said second lead pattern is located in a first portion of said third route track adjacent said first portion of the first route track;
performing a second trench etch process to form a plurality of second interconnect trenches in said plurality of second exposed areas;
forming a third interconnect pattern creating a plurality of third exposed areas including a third lead pattern located in said second route track, wherein said third lead pattern is separated from said first lead pattern by a distance of less than one and one-half times a space between said first lead pattern and said second lead pattern;
wherein said first interconnect pattern, said second interconnect pattern and said third interconnect pattern are formed using three distinct photolithography processes which have a dipole illumination source capable of resolving patterns in alternate instances of said plurality of parallel route tracks and not capable of resolving patterns in immediately adjacent instances of said plurality of parallel route tracks;
performing a third trench etch process to form a plurality of third interconnect trenches in said plurality of third exposed areas; and
forming metal interconnect lines in said first interconnect trenches, said second interconnect trenches and said third interconnect trenches.
9. The process of claim 8, wherein no first exposed regions are formed in an adjacent first portion of said first route track.
10. The process of claim 9, wherein said plurality of second exposed areas includes a fourth lead pattern located in said adjacent first portion of the first route track.
11. The process of claim 8, in which the first lead pattern terminates at a first point.
12. The process of claim 8, in which the first lead pattern branches at a first point.
13. The process of claim 12, in which said first lead pattern branches to form a crossover.
14. The process of claim 8, in which said dipole illumination source provides 193 nanometer radiation; and said pitch distance is 40 to 42 nanometers.
15. A process of forming an integrated circuit, comprising the steps of:
forming a dielectric layer over a substrate;
defining a plurality of parallel route tracks in said dielectric layer having a pitch distance;
forming a first interconnect pattern creating a plurality of first exposed areas in said plurality of parallel route tracks wherein each of said first exposed areas is physically separated from all other instances of said plurality of first exposed areas by a distance greater than said pitch distance;
performing a first trench etch process to form a first plurality of trenches in said plurality of first exposed areas;
forming a second interconnect pattern creating a plurality of second exposed areas in said plurality of parallel route tracks wherein each of said second exposed areas is physically separated from all other instances of said plurality of second exposed areas by a distance greater than said pitch distance;
performing a second trench etch process to form a second plurality of trenches in said plurality of second exposed areas;
forming a third interconnect pattern creating a plurality of third exposed areas in said plurality of parallel route tracks, each of a subset of said plurality of third exposed areas being separated from a corresponding first exposed area by a lateral distance less than one and one-half times a space between adjacent instances of interconnect patterns in said parallel route tracks, wherein each of said third exposed areas is physically separated from all other instances of said plurality of third exposed areas by a distance greater than said pitch distance;
wherein said first interconnect pattern, said second interconnect pattern and said third interconnect pattern are formed using three distinct photolithography processes which have a dipole illumination source capable of resolving patterns in alternate instances of said parallel route tracks and not capable of resolving patterns in immediately adjacent instances of said parallel route tracks;
performing a third trench etch process to form a third plurality of trenches in said plurality of third exposed areas; and
forming metal interconnect lines in said first plurality of interconnect trenches, said second plurality of interconnect trenches and said third plurality of interconnect trenches.
16. The process of claim 15, wherein a subset of said plurality of second exposed areas are each located in an instance of said plurality of parallel route tracks immediately adjacent to a corresponding first exposed region.
17. The process of claim 15, in which said illumination source provides 193 nanometer radiation; and said pitch distance of said parallel route tracks is 40 to 42 nanometers.
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