JP4945367B2 - Apparatus and method for separating a circuit pattern into a plurality of circuit patterns - Google Patents

Description

[0001] This application claims priority to US Provisional Patent Application No. 60 / 837,325, filed Aug. 14, 2006, which is incorporated herein by reference.

The present disclosure generally relates to a multi-patterning exposure method. In particular, the present invention relates to a method for separating a high-density circuit pattern into a lower-density circuit pattern for multi-patterning exposure.

[0003] Double patterning is currently a very researched theme. In general, double patterning is an exposure method that involves splitting (i.e., dividing or separating) a high density circuit pattern into two separate lower density patterns. The simplified pattern is then printed separately onto the target wafer using two separate masks (one mask is used to image one lower density pattern and the other The mask is used to image the other lower density pattern). In addition, a second pattern is printed between the lines of the first pattern, so that the imaged wafer has a feature pitch that is half that found, for example, in either of the two masks. This technique effectively reduces the complexity of the lithographic process, improves the achievable resolution, and allows printing of features that are much smaller than would otherwise be possible.

[0004] Although it may be easy to determine how to separate a line space pattern into two separate masks, it is very difficult to determine how to separate a complex logical design into separate masks There is. Current methods of performing the separation process are usually complex, may not be able to resolve conflicts, and may require intervention.

[0005] Accordingly, it is an object of the present invention to provide a method and apparatus for automatically dividing a complex circuit pattern into two or more less complex masks in an efficient and effective manner.

[0006] The present disclosure discloses a plurality of circuit patterns that are each imaged using an original circuit pattern to be printed on a wafer, using a separate mask dedicated to one of the less complex circuit patterns. The present invention relates to a method, an apparatus, and a computer-readable storage medium for storing a program therefor. According to the present invention, circuit pattern data (e.g., of a target pattern) is acquired, and then image quality of an image log slope (ILS), normalized image log slope (NILS), or polygon edge of the target circuit pattern. Run a simulation to get other features. Next, properly printed edges and improperly printed edges are identified according to the ILS level of any edge. When the process is completed, the original circuit pattern is separated into a plurality of circuit patterns. Here, each of the plurality of circuit patterns has no improperly printed edges, and each of the plurality of circuit patterns is imaged using a separate mask.

[0007] In one aspect, the step of dividing selects a first polygon having a first improperly printed edge from among the polygons defined by the target pattern, and the first improperly Finding at least one second polygon having a second improperly printed edge opposite the printed edge. Based on the topology criteria, it is determined whether the second polygon can be separated from the first polygon, and the topology criteria is, for example, one first improperly printed edge and 2n opposite second improper Are the edges (n: integer) printed on. The topology criteria may vary with different multi-patterning exposure methods. If it is determined that the second polygon can be separated (i.e., does not meet the topology criteria), the second polygon can be separated from the first polygon and placed on separate masks. On the other hand, if the topology criterion is met, the second polygon cannot be separated from the first polygon. Such improperly printed edges are then used to identify features that contradict neighboring features. One of these conflicting features is then moved to a separate mask to resolve the conflict. This process is repeated until all inconsistencies in the target pattern defined by improperly printed edges are resolved.

[0008] Although the text specifically refers to the use of the present invention in the manufacture of ICs, it should be clearly understood that the present invention has other applications. For example, this is an integrated optical device, guidance and detection pattern for magnetic domain memory, flat panel display, liquid crystal display panel, thin film magnetic head, and the like. In light of these alternative applications, where the terms “reticle”, “wafer” or “die” are used herein, the terms “mask”, “substrate” or “target portion”, respectively, It will be apparent to those skilled in the art that they may be considered synonymous with general terms.

[0009] The invention itself, along with further objects and advantages, will be better understood by reference to the following detailed description and drawings.

[0041] The present disclosure divides a dense circuit pattern (ie, target pattern) into two separate circuit patterns (but not limited to) that are imaged using separate masks in a double patterning exposure process ( Indicates how to split or divide. FIG. 1 is an exemplary flowchart illustrating a process of splitting or separating a circuit pattern (ie, a target pattern) into first and second patterns that can be used to form separate masks. The first step of the process, step S10, is to obtain the GDS (graphic data system) of the target pattern, ie the industry standard file format of the mask layout information. FIG. 2 is an exemplary diagram showing an original circuit pattern or a target pattern. In the subsequent steps, this circuit pattern is fragmented and divided into two mask patterns. The target pattern shown in FIG. 2 is defined or represented using a polygon 50, which is a standard way of representing the features of the target pattern.

[0042] The second step of the process, step S12, is by executing a simulation process that obtains the image log slope (ILS) or normalized log slope (NILS) of the edges of the polygon 50 based on the GDS data. is there. However, it will be appreciated that the target pattern may be subjected to OPC (Optical Proximity Effect Correction) or RET (Super Resolution Technique) before performing the simulation process. The logarithmic gradient of the aerial image is called ILS, which represents the energy (intensity) gradient at the position of the line edge of the polygon 50. ILS is a known metric that is used to determine the performance of an imaging tool when imaging any feature of a target pattern. As is known, ILS can be used to determine / quantify when a feature is properly imaged (eg, features with a corresponding ILS value lower than any number are acceptable Features that have an ILS greater than any value that are not printed within possible error tolerances are printed in an acceptable manner).

[0043] The third step in the process, step S14, is to determine whether there are misprinted edges of polygon 50 that cannot be properly printed on the wafer according to the corresponding ILS level. The given example uses ILS as the primary criterion, but these can indicate the robustness of the printed features, such as NILS, aerial image contrast, and EPE (edge placement error). Although not limited, other criteria that can determine imaging performance can also be used. FIG. 3 is a diagram exemplarily showing the result of step 14, showing a misprinted edge 52 of the polygon 50. A misprinted edge is an edge that is too close to the opposing edge, for example when printing a circuit pattern on a wafer, and thus neither edge is properly imaged. In order to find the misprinted edge 54, the process analyzes the ILS level of the edge, determines the interval of the misprinted edge (ie, an edge having an ILS level value lower than the minimum value), and the good edge (ie, the minimum acceptable ILS value The edge of the edge having a large ILS is determined. A good edge is an edge that has been properly printed on the wafer without interfering with or being affected by the printing of the opposite edge. Therefore, polygon 50 is fragmented and divided into two separate mask patterns so that the distance between the edges is greater than the minimum resolution of any process.

[0044] If it is determined in the third step that there is no misprinted edge, the process ends. If there are remaining misprinted edges, the process proceeds to the next step.

[0045] The fourth step of the process, step S16, is to perform an ILS-based pre-split fragmentation simulation. This step fragments the polygon 50 of FIG. 3 into smaller polygons in preparation for dividing the circuit pattern into two mask patterns. FIG. 4 is an exemplary diagram showing polygons after pre-split fragmentation based on ILS, where misprinted edges 52 (see FIG. 3) have been converted into fragments 54a-54n.

[0046] FIGS. 5A-5B exemplarily illustrate pre-split fragments based on the ILS of this embodiment. FIG. 5A shows the initial design corresponding to the target circuit pattern. FIG. 5B shows a circuit pattern having a misprint edge 52 identified as a result of the simulation (see FIG. 3) executed in step S12. FIG. 5C shows a fragment 54 (dotted line region) converted from the misprint edge 52. As described further below, the size (ie, width) of the fragment 54 is determined according to the proximity range from the opposing edge (see dotted circles or ellipses in FIGS. 7 and 8). If a polygon edge is located within the minimum proximity or resolution range of the opposing edge, that edge will adversely affect or overlap the opposing edge when printed on the wafer, so both edges will print properly. Not. Thus, regions of the target pattern that are within any proximity of the opposing edge are converted into fragments 54, thus separating the fragments 54 from the polygon 50 as necessary, as discussed in more detail below. It is possible to move to the mask pattern. FIG. 5C shows such a fragment 54.

[0047] The sixth step of the process, that is, step S18 is to determine whether the currently executing process is in the first loop of the flowchart. If the first loop is being executed, the process proceeds to step S22. If the loop being executed is not the first loop, the process proceeds to step S20. In this example, assuming that the first loop is being executed, the process proceeds to step S22.

[0048] The seventh step of the process, step S22, is to perform a "new single seed" procedure. FIG. 6 shows the selection of seed fragments with misprinted edges. In this example, the fragment located at the corner of the circuit pattern is given priority to become a seed fragment, but is not limited to this fragment. Needless to say, any fragment can be selected as a seed fragment. Here, a seed fragment is defined as one fragment that has at least one misprinted edge from which one or more other fragments can be separated from the polygon 50. In FIG. 6, a fragment 54a having a misprint edge 52a is selected as a seed fragment.

[0049] The eighth step of the process, step S24, is to look for fragments with misprinted edges opposite the seed polygon. In FIG. 6, fragment 54b has a misprint edge 52b opposite to misprint edge 52a of seed fragment 54a. Thus, fragment 54b is selected as the opposing fragment and is analyzed to determine if this fragment can be separated from polygon 50 and moved to the second mask pattern.

[0050] The ninth step of the process, step S26, is to determine whether the opposing fragment can be separated from the original polygon. 7 to 11 exemplarily show the topology criteria for which circuit patterns can be divided. This example introduces a graph that is used to determine if fragments can be separated.

[0051] FIG. 7 shows four polygons 60a to 60d, each having a misprinted edge. Misprinted edges 62a through 62f are identified based on the ILS level. Dotted areas I to VI represent the fragments described according to FIGS. 4 and 5C. The dotted circle and ellipse in FIG. 7 indicate the proximity range from the opposite edge. As briefly described above, the sizes of fragments I to VI are determined according to such proximity ranges from the corresponding opposing edges. The determination of the proximity range can be performed by moving the opposing polygon away from the evaluation edge and repeating the ILS (or other) simulation. The range obtained based on such a determination that the simulated ILS is below the printability threshold is the proximity range (dotted circle). This process can be simplified by setting a proximity range equal to the minimum print pitch. For example, if the minimum feature size (minimum design criterion) is equal to the minimum space, a bad edge in the polygon may expand by the minimum feature size (minimum design criterion).

In FIG. 7, polygon 60a overlaps polygons 60b, 60c and 60d, respectively, and polygons 60b and 60c have no overlapping edges. For example, in order to avoid the edge of the polygon 60a overlapping the opposite edge of the polygon 60b, the fragment I or fragment II needs to be moved to another mask pattern.

[0053] Graphs 64a and 64b shown in FIG. 7 represent the relationships of the polygons 60a to 60d in this example. In graphs 64a and 64b, nodes n1 to n5 correspond to fragments I to VI of polygons 60a to 60d, and edges e1 to e3 are in the spaces between edges 62a and 62b, 62c and 62d, and 62e and 62f, respectively. Correspond. For example, fragments I and II are placed, and there is a space between them where the proximity ranges from edges 62a and 62b overlap (ie, are too close to each other). This is shown by a graph 63a having two nodes n1 and n2 connected by one edge e1.

[0054] The graph 64b has three nodes n3 to n5 corresponding to the fragments III, IV and VI. All misprinted edges of fragments that overlap within a polygon can be considered as one edge. Accordingly, the misprinted edges 62c and 62e of the fragments III and V are regarded as one edge and are processed as the node n3 of the graph 64b. Node n3 and node n4 are connected by edge e2, and node n3 and node n5 are connected by edge e3. However, the nodes n4 and n5 are not connected by any edge. This is because polygons 60c and 60d do not have misprinted edges opposite to each other.

[0055] FIG. 8 shows an example of four polygons 60e to 60h similar to the polygon of FIG. The difference between the polygon of FIG. 8 and that of FIG. 7 is that polygons 60f and 60g do not have mutually misprinted edges, and the proximity range from polygon 60e covers both polygons 60f and 60g. It is. Since all misprinted edges of fragments that overlap within polygon 60e can be considered as one edge according to any process example rule, the edges of fragments VII and X are considered as one node. That is, it is the node n6 of the graph 64c. The edge of the polygon 60f facing each of the polygons 60e and 60g is regarded as one edge, and is processed as the node n7 of the graph 64c. The edge of the polygon 60g that faces the edges of the polygons 60e and 60g is also regarded as one edge and is processed as the node n9. The edge of the polygon 60h facing each polygon 60e is processed as a node n8. In graph 64c, node n6 is connected to node n7 by edge e4, connected to node n9 by edge e5, and connected to node n8 by edge e7. Node n7 is also connected to node n9 by edge e6.

[0056] Note that all the edges of the polygon indicated by the arrows in FIG. 5C can be considered as one edge, resulting in one node in the graph. This is because in this example the polygon is within the proximity of each edge (resulting in imaging interference).

[0057] In the above graph, which configuration of nodes can be divided, that is, whether a specific polygon (for example, the opposing fragment 54b in FIG. 6) can be separated from another polygon (for example, the fragment 54a in FIG. 6). These topology standards are shown. This process is described with respect to FIGS. 9A-9D.

[0058] As shown in FIG. 9A, if the graph has two nodes n1 and n2 connected by one edge e1, divide the two nodes into separate masks and then image them separately be able to. Numbers “1” and “2” in FIG. 9A indicate masks to which nodes n1 and n2 are assigned, respectively. That is, the node n1 is assigned to the first mask pattern, and the node n2 is assigned to the second mask pattern.

[0059] FIG. 9B shows an exemplary triangular graph with three nodes n1-n3 and three edges e1-e3 (a triangular loop of nodes). This graph shows that the nodes n1 to n3 cannot be divided from each other by the double patterning exposure method. For example, assuming that nodes n1 and n2 are assigned to the first and second mask patterns, respectively, there is no mask pattern to which node n3 is assigned. That is, when nodes n1 and n3 are assigned to the first mask pattern and node n2 is assigned to the second mask pattern, nodes n1 and n3, that is, two opposing polygonal edges overlap each other on the wafer. Cannot print properly.

[0060] FIG. 9C shows an exemplary square graph having four nodes n1-n4 and four edges e1-e4. In FIG. 9C, nodes n1 and n3 can be assigned to the first mask pattern, and nodes n2 and n4 can be assigned to the second mask pattern. Therefore, the graph of FIG. 9C shows that the nodes n1 to n4 can be divided into two mask patterns. FIG. 9D shows an exemplary pentagonal graph with five nodes n1-n5 and five edges e1-e5. Similar to the graph of FIG. 9B, this graph has the problem that node nt cannot be assigned to either the first mask pattern or the second mask pattern. This is because placing it on either the first or second mask causes interference with n3 or n4.

In summary, FIGS. 9A to 9D show that a circuit pattern cannot be divided into two mask patterns if the graph has triangles or pentagons formed by connecting nodes. In contrast, a graph having two edges e1 and e2 connecting three nodes n3-n5 and nodes n3 and n4, as shown in FIG. 7, represents two circuit patterns represented by such a graph. Indicates that it can be divided into mask patterns. This is because the graph of FIG. 7 does not have a triangular shape, that is, nodes n4 and n5 are not connected by an edge. For example, the polygon 60a can be assigned to the first mask pattern, and the polygon 60c can be assigned to the second mask pattern. Therefore, even if there are three nodes in the graph, it is possible to divide the circuit pattern into two patterns as long as the graph does not include three edges forming a triangle.

[0062] Note that the topology criteria may be altered by different multi-patterning exposure methods. A structure that cannot be divided by the double patterning method may be divided by the triple patterning method. FIG. 9E shows a tetrahedral configuration that can also be divided by triple patterning.

[0063] A more practical example will be discussed with respect to FIGS. 10A-10D. FIG. 10A shows two polygons p1 and p2 corresponding to a graph having two nodes n1 and n2 and one edge e1 (see FIG. 9A). One edge of the polygon p1 overlaps with one edge of the polygon p2. As already explained above, the graph shows that these polygons p1 and p2 can be divided into first and second mask patterns. FIG. 10B shows three polygons corresponding to a triangular graph (see FIG. 9B) with three nodes and three edges. These polygons p1, p2 and p3 cannot be divided into first and second mask patterns. This is because, as explained above, the graph has a triangle with three nodes and three edges. FIG. 10C shows four polygons p1-p4 corresponding to a square graph with four nodes and four edges (see FIG. 9C). In FIG. 10C, the diagonal corner-to-corner space pointed to by the arrow has sufficient space, so that nodes n2 and n4, and nodes n1 and n3 do not overlap or have proper imaging. Assume that they are not in close proximity to each other. Since the graph of FIG. 10C does not have a triangle or pentagon, the polygons p1 to p4 can be divided into two mask patterns. FIG. 10D shows four polygons p1-p4 corresponding to a square graph with four nodes and six edges. The graph of FIG. 10D has additional edges e5 and e6 that connect nodes n1 and n3 and nodes n2 and n4 diagonally, respectively. These additional edges indicate that the diagonal corner-to-corner space pointed to by the arrow does not have enough space to avoid overlapping the polygons p1-p4. Thus, for example, nodes n4 and n2 can be assigned to the first and second mask patterns, but there are no mask patterns that are assigned nodes n1 and n3 and do not cause interference. Therefore, the polygons p1 to p4 cannot be divided into two mask patterns.

FIG. 11A shows a graph in which all nodes are connected in order by edges to form a tree. This graph is referred to herein as a “graph tree”. The circuit design corresponding to this graph tree can be divided into two mask patterns. In contrast, the graph shown in FIG. 11B is not a graph tree because it has a closed loop, eg, a pentagon, within itself. The circuit design corresponding to the graph of FIG. 11B cannot be divided into two mask patterns. The definition of the graph tree is that all nodes are connected by edges, but there is no loop with an odd number of nodes. As described above, FIG. 6 illustrates selecting a seed fragment to divide the circuit pattern into two mask patterns. This concept of using seed fragments is derived from the graph tree of FIG. 11A. For example, assume that the fragment corresponding to the node n1 in FIG. 11 is selected as the seed fragment (step S22 in FIG. 1), and the fragment corresponding to the node 2 is selected as the opposite fragment (S24 in FIG. 1). Thus, the opposing fragments are separated and assigned to a second mask pattern (described below). This is because the seed fragment and the opposite fragment can be explained by the graph shown in FIG. 10A. Next, the fragment corresponding to the node n3 is selected as the next seed fragment (S20 in FIG. 1 described below), and the fragment corresponding to the node 4 is selected as the opposite fragment and separated (described below). S32 and S34 in FIG.

Returning to FIG. 1, in step S26, the fragment can be divided into first and second mask patterns, for example, unless the topology criteria shown in FIGS. 10B and 10D exist, for example. That is, the edges of the graph corresponding to the seed fragment and one or more opposing fragments connect to odd nodes to form a loop (triangle, pentagon, etc.) that divides these fragments into two circuit patterns. I can't. Referring to FIG. 6 again, since the seed fragment 54a and the opposite fragment 54b do not connect to an odd number of nodes and do not form a loop, the seed fragment 54a and the opposite fragment 54b can be divided into first and second mask patterns. . If the seed fragment 54a and the opposing fragment 54b cannot be split, the process can be aborted or a flag for these fragments can be generated and proceeding to the next step in such a situation. The original target mask pattern needs to be redesigned or the tolerance is adjusted if possible. On the other hand, if the fragment can be split, the process proceeds to step S28 of FIG.

[0066] The tenth step of the process, ie, step S28, separates the opposing fragment 54b from the polygon 50 and assigns it to the second mask pattern to position the opposing fragment 54b (dotted line) as shown in FIG. It is to keep. The eleventh step of the process, step S30, is to save / store the first mask from which fragment 54b has been removed and the second mask to which fragment 54b has been added. The process then returns to step S12 and enters the second loop to repeat the above process until all polygons 50 with misprinted edges (54d-54n) have been processed.

More specifically, in step S18, the process determines whether the current process is in the first loop of the flowchart of FIG. Since the second loop of the process is currently being executed, the process proceeds to step S20 to determine whether there is a fragment with a misprint edge facing the separated fragment 54b. As shown in FIG. 12, since there is a fragment 54c opposite the separated fragment 54b, the process proceeds to step 32 to perform the “seed opposite fragment” procedure to identify fragment 54c as a seed fragment. In step S34, it is determined whether there is an opposing fragment. However, the fragment 54c has no opposing fragment (see FIG. 13). It can be said that the seed fragment 54c corresponds to, for example, the node n4 in FIG. 11A (the node n4 is not connected to the node n5 by an edge, for example). Accordingly, the process proceeds to step 22 to select a new seed fragment.

[0068] As described above, any fragment can be selected as a seed fragment. Following the exemplary rule of selecting a corner fragment as a seed fragment, fragment 54b becomes a seed fragment as shown in FIG. The process proceeds to step S24 and looks for a fragment with a misprinted edge facing the seed fragment 54b. Fragment 54e may be an opposing fragment. The process analyzes the graph relating to the fragments 54d and 54e to determine whether the topology condition is met (step S26). Therefore, since the seed fragment 54d and the opposing fragment 54e are considered to have a graph as shown in FIG. 10A, the opposing fragment 54e can be separated from the polygon 50. Next, in steps S28 and S30, the process moves the fragment 54e to the second mask pattern as shown in FIG. 15, and the modified first mask pattern (ie, fragment 54e has been removed) and the modified second pattern. (That is, the fragment 54e is added).

FIG. 16 shows a circuit pattern after pre-split fragmentation based on ILS in step S16 of the third loop. In step S20, the process determines whether there is a fragment having a misprint edge facing the fragment 54e moved to the second mask pattern in the second loop. As shown in FIG. 17, the process searches for a fragment 54f that was a fragment having a misprint edge facing the fragment 54e in the previous loop (step S20). Accordingly, the process proceeds to step S32, where the “seed opposite the polygon in the second mask” procedure is executed, where fragment 54f is selected as the seed fragment. Next, the process proceeds to step S34 to determine whether there is a fragment having a misprint edge facing the seed fragment 54f. The process looks for a fragment 54g that faces the misprinted edge of the seed fragment 54f. Since the graph acquired in step S16 for the fragments 54f and 54g is regarded as the graph shown in FIG. 10A (step S26), the opposing fragment 54g can be moved to the second mask pattern as shown in FIG. (Step S28).

FIG. 19 shows a circuit pattern after pre-split fragmentation based on ILS in step S16 of the fourth loop. The fragmentation step is performed after moving the fragment 54g to the second mask pattern. Since there was no fragment with a misprinted edge facing fragment 54g that moved to the second mask in the previous loop (step S20), the process proceeds to step S22 and performs the “new single seed” procedure (FIG. 11A, (See the end of the graph tree). In step S22, the fragment 54h having a misprint edge is selected as a seed fragment (FIG. 20). The process looks for a fragment 54i having a misprinted edge facing the seed fragment 54h (step S24), determines whether the fragment 54i can be moved to the second mask (step S26), and then as shown in FIG. Is moved to the second mask (step S28).

FIG. 22 shows a circuit pattern after pre-split fragmentation based on ILS in step S16. The fragmentation step is performed after moving fragment 54i to the second mask. Since there was a fragment 54j with a misprinted edge facing the fragment 54i that was moved to the second mask in the previous loop (step S20), the process proceeds to step S32 and performs the "seed facing the second mask" procedure. To do. In step S32, the fragment 54j having a misprint edge is selected as a seed fragment (FIG. 23). The process also searches for a fragment 54k having a misprint edge facing the seed fragment 54j (step S24), determines whether the fragment 54k can be moved to the second mask (step S26), and then the fragment is shown in FIG. To the second mask (step S28).

FIG. 25 shows a circuit pattern after pre-split fragmentation based on ILS in step S16. The fragmentation step is performed after moving fragment 54k to the second mask. Since there was no fragment with a misprinted edge facing fragment 54k moved to the second mask in the previous loop (step S20), the process proceeds to step S22 and performs the “new single seed” procedure. In step S22, the fragment 54l having a misprint edge is selected as a seed fragment (FIG. 26). The process also searches for a fragment 54m having a misprint edge facing the seed fragment 54l (step S24), determines whether the fragment 54m can be moved to the second mask (step S26), and then the fragment is shown in FIG. To the second mask (step S28).

[0073] After moving fragment 54m to the second mask pattern, the process executes steps S12 and S14 to determine that the circuit pattern has no misprinted edges as shown in FIG. Therefore, the process ends. FIG. 29 shows the final result of dividing the original circuit pattern into two circuit patterns. The shaded polygon is assigned to the second mask and the other polygons are assigned to the first mask. OPC can be performed with two circuit patterns, and these two masks are used in the double patterning process.

[0074] According to the above-described embodiments, the present disclosure can provide a position and a method for separating circuit patterns, and an algorithm for separating a circuit pattern into a plurality of circuit patterns. With the disclosed embodiments, an automated design of (for example) two masks of any target pattern can be used in a double patterning process. Thus, the disclosed method is time efficient and minimizes the need for design engineers skilled in the mask design process.

[0075] Divisibility checks based on robustness and process modeling can discover indivisible configurations in the early stages of design development and help the designer adjust them. This is because the simulation shows all critical spaces and pitches based on actual process resolution.

[0076] Partitioning based on the model allows design decomposition without errors. The split decision is performed according to the actual process resolution. Thus, it is expected that unnecessary splitting is not possible and no features are not split. Even unexpected configurations of polygons can be segmented based on process simulation. Although the rule-based partitioning method suffers from complex and unexpected design influences, the proposed model-based pitch decomposition does not have this problem. Model-based partitioning also allows for the discovery and adjustment of “limit pitch”, ie, pitches that are larger than the minimum, with a reduced process window.

FIG. 30 is a block diagram that illustrates a computer system 100 that can implement the processes described and disclosed above. Computer system 100 includes a bus 102 or other communication mechanism for communicating information, and a processor 104 coupled with bus 102 for processing information. Computer system 100 also includes a main memory 106 such as a random access memory (RAM) or other dynamic storage device coupled to bus 102 for storing information and instructions executed by processor 104. Main memory 106 may also be used to store temporary variables or other intermediate information during execution of instructions executed by processor 104. Computer system 100 further includes a read only memory (ROM) 108 or other static storage device coupled to bus 102 for storing static information and instructions for processor 104. A storage device 110, such as a magnetic disk or optical disk, is provided and coupled to the bus 102 for storing information and instructions.

[0078] The computer system 100 can be coupled via a bus 102 to a display 112, such as a cathode ray tube (CRT) or flat panel or touch panel display, for displaying information to a computer user. An input device 114, including alphanumeric characters and other keys, is coupled to the bus 102 for communicating information and command selections to the processor 104. Another type of user input device is a cursor control device 116 such as a mouse, trackball, or cursor direction key that communicates direction information and command selections to the processor 104 and controls cursor movement on the display 112. . This input device typically has two degrees of freedom in two axes, a first axis (eg, x) and a second axis (eg, y), allowing the device to specify a position in a plane. A touch panel (screen) display can also be used as an input device.

[0079] According to one embodiment of the invention, the disclosed process is responsive to a processor 104 executing one or more instructions of one or more sequences contained in a main memory 106, in a computer system. 100. Such instructions can be read into main memory 106 from another computer readable medium, such as storage device 110. When executing the sequence of instructions contained in main memory 106, processor 104 performs the steps of the processes described herein. One or more processors in a multi-processing configuration can also be used to execute a sequence of instructions contained in main memory 106. In alternative embodiments, fixed wiring circuitry may be used in place of or in combination with software instructions to implement the present invention. Thus, embodiments of the invention are not limited to a specific combination of hardware circuitry and software.

[0080] The term "computer-readable medium" as used herein refers to any medium that participates in providing instructions to processor 104 for execution. Such media take many forms, including but not limited to, non-volatile media, volatile media, and transmission media. Non-volatile media includes, for example, optical or magnetic disks, such as storage device 110. Volatile media includes dynamic memory, such as main memory 106. Transmission media includes coaxial cables, copper wire and optical fiber, and includes a line consisting of bus 102. Transmission media can take the form of acoustic or light waves, such as those generated during radio frequency (RF) and infrared (IR) data communications. Common forms of computer readable media are, for example, floppy disks, flexible disks, hard disks, magnetic tapes, any other magnetic media, CD-ROM, DVD, any other optical media, punch cards, paper tapes, holes Any other physical medium with patterns, RAM, PROM, and EPROM, FLASH-EPROM, any other memory chip or cartridge, carrier wave as described below, or any other medium that can be read by a computer including.

[0081] Various forms of computer readable media may be involved in carrying one or more sequences of one or more instructions to processor 104 for execution. For example, the instructions can initially be carried on a remote computer magnetic disk. The remote computer can load the instructions into dynamic memory and send the instructions over a telephone line using a modem. A modem local to computer system 100 can receive the data on the telephone line and use an infra-red transmitter to convert the data to an infra-red signal. An infrared detector coupled to bus 102 can receive the data carried in the infrared signal and place the data on bus 102. Bus 102 carries data to main memory 106, from which processor 104 retrieves and executes instructions. The instructions received by main memory 106 may optionally be stored on storage device 110 either before or after execution by processor 104.

[0082] Computer system 100 also preferably includes a communication interface 118 coupled to bus 102. Communication interface 118 provides a two-way data communication coupling to network link 120 connected to local network 122. For example, the communication interface 118 may be an Integrated Services Digital Network (ISDN) card or modem that provides a data communication connection to a corresponding type of telephone line. As another example, communication interface 118 may be a local area network (LAN) card that provides a data communication connection to a compatible LAN. A wireless link can also be implemented. In any such implementation, communication interface 118 sends and receives electrical, electromagnetic or optical signals that carry digital data streams representing various types of information.

[0083] The network link 120 typically provides data communication through one or more networks to other data devices. For example, the network link 120 may provide a connection to a host computer 124 through the local network 122 or to data equipment operated by an Internet service provider (ISP) 126. ISP 126 provides data communication services through a global packet data communication network now commonly referred to as the “Internet” 128. Local network 122 and Internet 128 both use electrical, electromagnetic or optical signals that carry digital data streams. Signals passing through various networks and carrying digital signals to and from the computer system 100 over the network link 120 and through the communication interface 118 are exemplary forms of carrier waves that carry information.

[0084] The computer system 100 can send messages and receive data, such as program code, through the network, the network link 120, and the communication interface 118. In the Internet example, the server 120 may transmit the code of the requested application program over the Internet 128, ISP 126, local network 122 and communication interface 118. According to the present invention, one such downloaded application provides, for example, the disclosed process of the embodiment. The received code may be executed by the processor 104 as received and / or stored in the storage device 110 or other non-volatile storage for later execution. In this manner, computer system 100 can obtain application code in the form of a carrier wave.

[0085] Figure 31 schematically depicts a lithographic projection apparatus suitable for use with a mask designed with the aid of the present invention. The device
A radiation system Ex, IL configured to adjust the radiation projection beam PB, in this particular case also comprising a radiation source LA;
A first object table (mask table) MT provided with a mask holder for holding a mask MA (eg a reticle) and connected to a first positioning means for accurately positioning the mask with respect to the item PL;
A second object table (substrate table) WT provided with a substrate holder for holding the substrate W (eg resist-coated wafer) and connected to second positioning means for accurately positioning the substrate with respect to the item;
A projection system (“lens”) PL (eg a refractive, reflective or catadioptric optical system) that images the irradiated part of the mask MA onto a target part C (eg containing one or more dies) of the substrate W

The apparatus shown here is of a transmissive type (ie has a transmissive mask). However, in general this may for example be of the reflective type (with a reflective mask). Alternatively, the apparatus may use another type of patterning means as an alternative to the use of a mask, examples of which include a programmable mirror array or LCD matrix.

[0087] The radiation source LA (eg, a mercury lamp or excimer laser) generates a radiation beam. This beam is supplied to the illumination system (illuminator) IL either directly or after traversing adjustment means such as, for example, a beam expander Ex. The illuminator IL may comprise adjusting means AM for setting the outer and / or inner radius range (commonly referred to as σ-outer and σ-inner, respectively) of the intensity distribution of the beam. It may also comprise various other components such as an integrator IN and a capacitor CO. In this way, the beam PB impinging on the mask MA has the desired uniformity and intensity distribution across its cross section.

[0088] With reference to FIG. 31, the radiation source LA may be within the housing of the lithographic projection apparatus (as is often the case when the source LA is, for example, a mercury lamp) but is remote from the lithographic projection apparatus and is generated. May be guided into the device (eg with the aid of a suitable guiding mirror), the latter scenario being when the source LA is an excimer laser (eg based on a KrF, ArF or F ₂ laser) Please note that there are many.

Thereafter, the beam PB intersects with the mask MA held on the mask table MT. The beam PB passes through the mask MA and passes through a lens PL that focuses the beam PB onto the target portion C of the substrate W. With the aid of the second positioning means (and the interferometer measuring means IF), the substrate table WT can be accurately moved to position various target portions C, for example in the path of the beam PB. Similarly, the first positioning means can be used to accurately position the mask MA with respect to the path of the beam PB, for example after mechanical retrieval from a mask library or during a scan. In general, the movement of the object tables MT and WT can be realized with the help of a long stroke module (coarse positioning) and a short stroke module (fine movement positioning) which are not illustrated in FIG. However, in the case of a wafer stepper (as opposed to a scanning step tool), the mask table MT may be connected only to a short stroke actuator or fixed.

[0090] The illustrated tool can be used in two different modes.
In step mode, the mask table MT is basically kept stationary, and the entire pattern is projected onto the target portion C in one go (ie one “flash”). Next, the substrate table WT is moved in the x and / or y direction so that another target portion C can be irradiated with the beam PB.
In scan mode, basically the same scenario applies, but any target portion C is not exposed in a single “flash”. Instead, the mask table MT can be moved at a velocity v in any direction (so-called “scan direction”, eg the y direction), so that the projection beam PB scans the image of the mask. At the same time, the substrate table WT moves in the same direction or in the opposite direction at a speed V = Mv. Here, M is the magnification of the lens PL (generally, M = 1/4 or 1/5). Thus, a relatively large target portion C can be exposed without compromising resolution.

[0091] While the invention has been described and illustrated in detail, it is to be understood that this is by way of illustration and example only and is not to be considered limiting, the scope of the invention being limited only by the claims. I want to be.

[0010] FIG. 4 is an exemplary flowchart illustrating a process of dividing one circuit pattern (that is, a target pattern) into two circuit patterns according to an embodiment of the present invention. [0011] FIG. 3 is an exemplary diagram showing an original circuit pattern (ie, a target pattern) according to an embodiment of the present invention. [0012] FIG. 5 is an exemplary diagram illustrating allowable and misprinted edges of a target pattern represented as a polygon according to an embodiment of the present invention. [0013] FIG. 5 is an exemplary diagram illustrating pre-split fragmentation based on ILS according to an embodiment of the present invention. [0014] (A) and (B) are exemplary diagrams illustrating pre-split fragmentation based on ILS according to an embodiment of the present invention. [0015] FIG. 5 is an exemplary diagram illustrating selection of seed fragments having misprinted edges and opposing fragments having misprinted edges, according to embodiments of the invention. [0016] FIG. 5 is an exemplary diagram and graph showing fragments according to one embodiment of the invention. [0017] FIG. 5 is an exemplary diagram and graph showing fragments according to one embodiment of the present invention. [0017] FIGS. 4A to 4E are exemplary diagrams illustrating topology criteria for explaining which circuit patterns can be divided according to an embodiment of the present invention. FIG. 6 is an exemplary diagram illustrating a topology criterion explaining which circuit patterns can be divided according to an embodiment of the present invention. [0019] FIGS. 4A to 4D are exemplary diagrams illustrating topology criteria for explaining which circuit patterns can be divided according to an embodiment of the present invention. FIG. 6 is an exemplary diagram illustrating a topology criterion explaining which circuit patterns can be divided according to an embodiment of the present invention. (A) and (B) are exemplary diagrams illustrating topology criteria for explaining which circuit patterns can be divided according to an embodiment of the present invention. [0021] FIG. 4 is an exemplary diagram illustrating the separation of opposing fragments from a polygon according to one embodiment of the invention. [0022] FIG. 5 is an exemplary diagram showing a circuit pattern after performing ILS-based pre-split fragmentation according to an embodiment of the present invention. [0023] FIG. 6 is an exemplary diagram illustrating selection of seed fragments with misprinted edges and opposing fragments with misprinted edges, according to one embodiment of the invention. [0024] FIG. 6 is an exemplary diagram illustrating selection of opposing fragments from a polygon according to one embodiment of the present invention. [0025] FIG. 6 is an exemplary diagram showing a circuit pattern after pre-split fragmentation based on ILS according to an embodiment of the present invention; [0026] FIG. 6 is an exemplary diagram illustrating selection of seed fragments with misprinted edges and opposing fragments with misprinted edges, according to one embodiment of the invention. [0027] FIG. 5 is an exemplary diagram illustrating the separation of opposing fragments from a polygon according to one embodiment of the invention. [0028] FIG. 6 is an exemplary diagram showing a circuit pattern after execution of ILS-based pre-split fragmentation according to an embodiment of the present invention. [0029] FIG. 6 is an exemplary diagram illustrating selection of seed fragments having misprinted edges and opposing fragments having misprinted edges, according to one embodiment of the present invention. [0030] FIG. 6 is an exemplary diagram illustrating the separation of opposing fragments from a polygon according to one embodiment of the present invention. [0031] FIG. 5 is an exemplary diagram showing a circuit pattern after execution of ILS-based pre-split fragmentation according to an embodiment of the present invention. [0032] FIG. 6 is an exemplary diagram illustrating selection of seed fragments having misprinted edges and opposing fragments having misprinted edges, according to one embodiment of the present invention. [0033] FIG. 6 is an exemplary diagram illustrating separation of opposing fragments from a polygon according to one embodiment of the present invention. [0034] FIG. 6 is an exemplary diagram showing a circuit pattern after execution of ILS-based pre-split fragmentation according to an embodiment of the present invention. [0035] FIG. 6 is an exemplary diagram illustrating selection of seed fragments having misprinted edges and opposing fragments having misprinted edges, according to one embodiment of the invention. [0036] FIG. 6 is an exemplary diagram illustrating the separation of opposing fragments from a polygon according to one embodiment of the present invention. [0037] FIG. 6 is an exemplary diagram showing a circuit pattern after performing pre-split fragmentation based on ILS according to an embodiment of the present invention; [0038] FIG. 5 is an exemplary diagram showing a polygon divided into two circuit patterns according to an embodiment of the present invention; [0039] FIG. 6 is an exemplary block diagram illustrating a computer system capable of implementing a process for obtaining optimized short-term flare model parameters according to an embodiment of the present invention. [0040] FIG. 1 schematically depicts an exemplary lithographic projection apparatus suitable for use with a mask designed with the aid of an embodiment of the invention.

Claims (22)

A method of separating an original circuit pattern to be printed on a wafer into a plurality of circuit patterns for double patterning using simulation ,
Obtaining circuit pattern data;
Executing a simulation for obtaining image quality information regarding polygonal edges in the circuit pattern based on the circuit pattern data;
Distinguishing between properly printed edges and improperly printed edges according to the image quality information, and only if there are improperly printed edges, the plurality of circuit patterns Separating the original circuit pattern into a plurality of circuit patterns such that each does not have an improperly printed edge. The separation step includes
Selecting a first polygon having a first improperly printed edge from among the polygons, and a second improper adjacent to and in close proximity to the first improperly printed edge Finding at least one second polygon with an edge printed on it,
Determining whether the second polygon can be separated from the first polygon based on a topology criterion as to which circuit pattern can be divided; and when determining that the second polygon can be separated, The method of claim 1, comprising separating a second polygon from the first polygon. The separation step, including the execution step, the identification step, and the selection step, the determination step, and the separation step, until no polygon with improperly printed edges is found in the original circuit pattern. 3. The method of claim 2, wherein the methods are performed in that order. The topology criterion is that at least the determining step has one first improperly printed edge and 2n second improperly printed edges (n: integer), and the first Determining whether the improperly printed edge and the second improperly printed edge are facing each other or both
4. The method of claim 3, wherein if the topology criteria is met, the separating step does not separate the second polygon from the first polygon. The selecting step selects a third polygon having a third improperly printed edge facing the separated second polygon, and further the third improper of the third polygon. Find a fourth polygon with a fourth improperly printed edge opposite the printed edge;
The determining step determines whether the fourth polygon can be separated from the third polygon based on the topology criterion;
The method according to claim 3, wherein the separating step separates the fourth polygon from the third polygon when it is determined that the fourth polygon can be separated. 6. The method of claim 5, wherein the selecting step selects any polygon with an improperly printed edge as the first polygon if there is no third polygon. The method of claim 1, wherein the image quality information is one of an image log slope (ILS) and a normalized image log slope (NILS). An apparatus for separating an original circuit pattern to be printed on a wafer into a plurality of circuit patterns for double patterning using simulation ,
A first unit configured to perform a simulation for obtaining image quality information relating to a polygonal edge of the circuit pattern obtained from circuit pattern data;
Only if there was a second unit configured to distinguish between improperly printed edges and improperly printed edges according to the image quality information, and improperly printed edges, An apparatus comprising a third unit configured to separate the original circuit pattern into a plurality of circuit patterns such that each of the plurality of circuit patterns does not have an improperly printed edge. The third unit further includes
Selecting a first polygon having a first improperly printed edge from among the polygons, and a second improper adjacent to and in close proximity to the first improperly printed edge Find at least one second polygon with edges printed on it,
Determining whether the second polygon can be separated from the first polygon based on a topology criterion on which circuit patterns can be divided;
Separating the second polygon from the first polygon when it is determined that the second polygon can be separated;
9. The apparatus of claim 8, configured as follows. The execution of the simulation, identification of the edge, selection of the first polygon, discovery of the second polygon, determination of whether the second polygon can be separated, and separation of the second polygon include the original polygon 10. The apparatus of claim 9, wherein the apparatus is executed in that order until no polygons with improperly printed edges are found in the circuit pattern. The topology criterion is that at least the third unit has one first improperly printed edge and 2n second improperly printed edges (n: integer), and the first Determining whether the improperly printed edge and the second improperly printed edge are facing each other or both
11. The apparatus of claim 10, wherein the third unit does not separate the second polygon from the first polygon when the topology criteria is met. The third unit further includes
Selecting a third polygon having a third improperly printed edge facing the separated second polygon, and further selecting the third improperly printed edge of the third polygon Find a fourth polygon with a fourth improperly printed edge opposite to
Determining whether the fourth polygon can be separated from the third polygon based on the topology criteria;
The apparatus of claim 10, wherein the apparatus is configured to separate the fourth polygon from the third polygon when it is determined that the fourth polygon can be separated. 13. The apparatus of claim 12, wherein the third unit selects all polygons with improperly printed edges as the first polygon when there is no third polygon. 9. The apparatus of claim 8, wherein the image quality information is one of an image log slope (ILS) and a normalized image log slope (NILS). A computer readable storage medium storing a computer program for separating a circuit pattern to be printed on a wafer into a plurality of circuit patterns for double patterning by using a simulation .
Obtaining circuit pattern data;
Executing a simulation for obtaining image quality information relating to a polygonal edge of the circuit pattern based on the circuit pattern data;
Distinguishing between properly printed edges and improperly printed edges according to the image quality information, and only if there are improperly printed edges, the plurality of circuit patterns A computer-readable storage medium that causes the original circuit pattern to be separated into a plurality of circuit patterns so that each does not have an improperly printed edge. The separation step includes
Selecting a first polygon having a first improperly printed edge from among the polygons, and a second improper adjacent to and in close proximity to the first improperly printed edge Finding at least one second polygon with an edge printed on it,
Determining whether the second polygon can be separated from the first polygon based on a topology criterion as to which circuit pattern can be divided; and when determining that the second polygon can be separated, The computer-readable storage medium of claim 15, comprising separating a second polygon from the first polygon. The separation steps including the execution step, the identification step, and the selection step, the determination step and the separation step are performed in that order until no polygons with improperly printed edges are found in the original circuit pattern. The computer-readable storage medium according to claim 15, wherein: The topology criterion is that at least the determining step has one first improperly printed edge and 2n second improperly printed edges (n: integer), and the first Determining whether the improperly printed edge and the second improperly printed edge are facing each other or both
The computer-readable storage medium of claim 17, wherein the separation step does not separate the second polygon from the first polygon when the topology criteria are met. The selecting step selects a third polygon having a third improperly printed edge, the third improperly printed edge facing the separated second polygon; And finding a fourth polygon having a fourth improperly printed edge opposite the third improperly printed edge of the third polygon;
Determining whether the fourth polygon can be separated from the third polygon based on the topology criterion;
The computer-readable storage medium according to claim 17, wherein the separation step separates the fourth polygon from the third polygon when it is determined that the fourth polygon can be separated. 20. The computer readable storage medium of claim 19, wherein the selecting step selects all polygons having improperly printed edges as the first polygon when there is no third polygon. The computer-readable storage medium of claim 15, wherein the image quality information is one of an image log slope (ILS) and a normalized image log slope (NILS). (A) providing a substrate at least partially covered with a radiation sensitive material layer;
(B) providing a radiation projection beam using the imaging system;
(C) using a pattern of a mask to provide a pattern in a cross section of the projection beam; and (d) projecting the patterned radiation beam onto a target portion of a radiation sensitive material layer,
Providing a mask pattern in step (c);
Separating the original circuit pattern to be printed on the wafer into a plurality of circuit patterns for double patterning using simulation,
Said separating is
Executing a simulation for obtaining the image quality information about the polygon edge of the circuit pattern acquired from circuitry pattern data,
Distinguishing between properly printed edges and improperly printed edges according to the image quality information, and each of the plurality of circuit patterns only when there are improperly printed edges. Separating the original circuit pattern into a plurality of circuit patterns that are assigned to the mask such that does not have improperly printed edges.