WO2012119098A3 - Pattern-split decomposition strategy for double-patterned lithography process - Google Patents

Pattern-split decomposition strategy for double-patterned lithography process Download PDF

Info

Publication number
WO2012119098A3
WO2012119098A3 PCT/US2012/027534 US2012027534W WO2012119098A3 WO 2012119098 A3 WO2012119098 A3 WO 2012119098A3 US 2012027534 W US2012027534 W US 2012027534W WO 2012119098 A3 WO2012119098 A3 WO 2012119098A3
Authority
WO
WIPO (PCT)
Prior art keywords
pattern
interconnect
point
double
route tracks
Prior art date
Application number
PCT/US2012/027534
Other languages
French (fr)
Other versions
WO2012119098A2 (en
Inventor
James Walter Blatchford
Original Assignee
Texas Instruments Incorporated
Texas Instruments Japan Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/410,188 external-priority patent/US8575020B2/en
Application filed by Texas Instruments Incorporated, Texas Instruments Japan Limited filed Critical Texas Instruments Incorporated
Priority to JP2013556909A priority Critical patent/JP6140616B2/en
Publication of WO2012119098A2 publication Critical patent/WO2012119098A2/en
Publication of WO2012119098A3 publication Critical patent/WO2012119098A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Wire Bonding (AREA)

Abstract

An integrated circuit may be formed by a process of forming a first interconnect pattern (208) in a plurality of parallel route tracks (206), and forming a second interconnect pattern (224) in the plurality of parallel route tracks. The first interconnect pattern (208) includes a first lead pattern which extends to a first point (216) in an instance of the first plurality of parallel route tracks, and the second interconnect pattern (224) includes a second lead pattern which extends to a second point (232) in the same instance of the plurality of parallel route tracks, such that the second point (232) is laterally separated from the first point (216) by a distance one to one and one-half times a space between adjacent parallel lead patterns in the plurality of parallel route tracks. A metal interconnect formation process is performed which forms metal interconnect lines in an interconnect level defined by the first interconnect pattern and the second interconnect pattern.
PCT/US2012/027534 2011-03-02 2012-03-02 Pattern-split decomposition strategy for double-patterned lithography process WO2012119098A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2013556909A JP6140616B2 (en) 2011-03-02 2012-03-02 Pattern division decomposition strategy for double patterned lithography process

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
US201161448447P 2011-03-02 2011-03-02
US201161448451P 2011-03-02 2011-03-02
US201161448423P 2011-03-02 2011-03-02
US201161448437P 2011-03-02 2011-03-02
US61/448,437 2011-03-02
US61/448,447 2011-03-02
US61/448,423 2011-03-02
US61/448,451 2011-03-02
US13/410,188 US8575020B2 (en) 2011-03-02 2012-03-01 Pattern-split decomposition strategy for double-patterned lithography process
US13/410,188 2012-03-01

Publications (2)

Publication Number Publication Date
WO2012119098A2 WO2012119098A2 (en) 2012-09-07
WO2012119098A3 true WO2012119098A3 (en) 2012-11-08

Family

ID=46758517

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/US2012/027534 WO2012119098A2 (en) 2011-03-02 2012-03-02 Pattern-split decomposition strategy for double-patterned lithography process
PCT/US2012/027554 WO2012119105A2 (en) 2011-03-02 2012-03-02 Hybrid pitch-split pattern-split litrography process

Family Applications After (1)

Application Number Title Priority Date Filing Date
PCT/US2012/027554 WO2012119105A2 (en) 2011-03-02 2012-03-02 Hybrid pitch-split pattern-split litrography process

Country Status (2)

Country Link
JP (2) JP6140616B2 (en)
WO (2) WO2012119098A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9583609B2 (en) * 2013-03-25 2017-02-28 Texas Instruments Incorporated MOS transistor structure and method of forming the structure with vertically and horizontally-elongated metal contacts
TWI721231B (en) * 2016-11-16 2021-03-11 日商東京威力科創股份有限公司 Methods of sub-resolution substrate patterning

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060277521A1 (en) * 2005-04-12 2006-12-07 Chen Jang F Method, program product and apparatus for performing double exposure lithography
US20070077523A1 (en) * 2005-10-05 2007-04-05 Asml Netherlands B.V. Method of patterning a positive tone resist layer overlaying a lithographic substrate
US20070249157A1 (en) * 2006-04-21 2007-10-25 Nec Electronics Corporation Semiconductor device and method for manufacturing same
US20080020296A1 (en) * 2006-04-06 2008-01-24 Hsu Duan-Fu S Method and apparatus for performing dark field double dipole lithography (DDL)

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5561317A (en) * 1990-08-24 1996-10-01 Canon Kabushiki Kaisha Method of manufacturing semiconductor devices
JP3050210B2 (en) * 1998-09-24 2000-06-12 株式会社ニコン Exposure bubble and device manufacturing method using the same
JP4109944B2 (en) * 2002-09-20 2008-07-02 キヤノン株式会社 Method for manufacturing solid-state imaging device
KR100861363B1 (en) * 2006-07-21 2008-10-01 주식회사 하이닉스반도체 Pattern decomposition method for Double Exposure
JP2006303541A (en) * 2006-07-28 2006-11-02 Renesas Technology Corp Method for manufacturing semiconductor integrated circuit device
JP4945367B2 (en) * 2006-08-14 2012-06-06 エーエスエムエル マスクツールズ ビー．ブイ． Apparatus and method for separating a circuit pattern into a plurality of circuit patterns
JP2008071838A (en) * 2006-09-12 2008-03-27 Nec Electronics Corp Method for manufacturing semiconductor device
JP5032948B2 (en) * 2006-11-14 2012-09-26 エーエスエムエル マスクツールズ ビー．ブイ． Method, program and apparatus for performing pattern decomposition used in the DPT process
JP2008311502A (en) * 2007-06-15 2008-12-25 Toshiba Corp Pattern forming method
JP5218227B2 (en) * 2008-12-12 2013-06-26 信越化学工業株式会社 Pattern formation method
KR101532012B1 (en) * 2008-12-24 2015-06-30 삼성전자주식회사 Semiconductor device and method of forming patterns for semiconductor device
JP5235719B2 (en) * 2009-02-27 2013-07-10 株式会社日立ハイテクノロジーズ Pattern measuring device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060277521A1 (en) * 2005-04-12 2006-12-07 Chen Jang F Method, program product and apparatus for performing double exposure lithography
US20070077523A1 (en) * 2005-10-05 2007-04-05 Asml Netherlands B.V. Method of patterning a positive tone resist layer overlaying a lithographic substrate
US20080020296A1 (en) * 2006-04-06 2008-01-24 Hsu Duan-Fu S Method and apparatus for performing dark field double dipole lithography (DDL)
US20070249157A1 (en) * 2006-04-21 2007-10-25 Nec Electronics Corporation Semiconductor device and method for manufacturing same

Also Published As

Publication number Publication date
WO2012119105A3 (en) 2012-11-15
JP2014510403A (en) 2014-04-24
JP6134652B2 (en) 2017-05-24
JP6140616B2 (en) 2017-05-31
WO2012119105A2 (en) 2012-09-07
JP2014509785A (en) 2014-04-21
WO2012119098A2 (en) 2012-09-07

Similar Documents

Publication Publication Date Title
WO2012047042A3 (en) Micro-pattern forming method, and micro-channel transistor and micro-channel light-emitting transistor forming method using same
TWI561138B (en) Method of manufacturing multi-layer printed wiring board and multi-layer printed wiring board obtained by the manufacturing method
PH12015502555A1 (en) Selective partitioning of via structures in printed circuit boards
WO2011159722A3 (en) Method of manufacturing conductive structures
MX2015017592A (en) Method for producing a multilayer element, and multilayer element.
EP2902115A4 (en) Pattern forming method, electronic wiring substrate, optical device, and pattern forming device
GB2487309A (en) Multiple width features in integrated circuits
EP3554200A4 (en) Core substrate, multilayer wiring substrate, semiconductor package, semiconductor module, copper-clad substrate, and method for producing core substrate
WO2014051511A3 (en) Electroless metal through silicon via
WO2012091373A3 (en) Method for manufacturing printed circuit board
FR2999746B1 (en) METHOD FOR GENERATING TOPOGRAPHY OF FDSOI INTEGRATED CIRCUIT
MX345686B (en) Tipping paper for a smoking article.
SG11201705165QA (en) Photomask blank, method for manufacturing photomask, and mask pattern formation method
TW200713422A (en) Semiconductor device having dummy pattern and method for manufacturing the same
EP2857899A4 (en) Photosensitive resin composition, photosensitive element, method for forming resist pattern, and method for producing wiring board
WO2010110987A3 (en) Methods of forming patterns on substrates
WO2015036287A3 (en) Method for producing a component
SG2014008841A (en) Overlay targets with orthogonal underlayer dummyfill
WO2012087073A3 (en) Printed circuit board and method for manufacturing same 인쇄회로기판 및 그의 제조 방법
EP2745657A4 (en) Conductive pattern, method for forming the same, printed wiring board, and manufacturing method of the same
WO2013032311A3 (en) Printing plate and method for manufacturing same
WO2012119098A3 (en) Pattern-split decomposition strategy for double-patterned lithography process
FR2973156B1 (en) METHOD FOR DECOMPOSING LINES OF AN ELECTRONIC CIRCUIT
TW201432370A (en) Phase shift mask and method for manufacturing the same
ITMI20130954A1 (en) STRUCTURAL ELEMENTER WITH THROUGH CONTACT AND PROCEDURE FOR THE RELATED PRODUCTION

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12752106

Country of ref document: EP

Kind code of ref document: A2

ENP Entry into the national phase

Ref document number: 2013556909

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12752106

Country of ref document: EP

Kind code of ref document: A2