WO2012119105A3 - Hybrid pitch-split pattern-split litrography process - Google Patents

Hybrid pitch-split pattern-split litrography process Download PDF

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Publication number
WO2012119105A3
WO2012119105A3 PCT/US2012/027554 US2012027554W WO2012119105A3 WO 2012119105 A3 WO2012119105 A3 WO 2012119105A3 US 2012027554 W US2012027554 W US 2012027554W WO 2012119105 A3 WO2012119105 A3 WO 2012119105A3
Authority
WO
WIPO (PCT)
Prior art keywords
pattern
split
parallel
lead pattern
interconnect
Prior art date
Application number
PCT/US2012/027554
Other languages
French (fr)
Other versions
WO2012119105A2 (en
Inventor
James Walter Blatchford
Original Assignee
Texas Instruments Incorporated
Texas Instruments Japan Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/410,145 external-priority patent/US8372743B2/en
Application filed by Texas Instruments Incorporated, Texas Instruments Japan Limited filed Critical Texas Instruments Incorporated
Priority to JP2013556653A priority Critical patent/JP6134652B2/en
Publication of WO2012119105A2 publication Critical patent/WO2012119105A2/en
Publication of WO2012119105A3 publication Critical patent/WO2012119105A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Wire Bonding (AREA)

Abstract

An integrated circuit may be formed by a process of forming a three interconnect patterns in a plurality of parallel route tracks (206), using photolithography processes which have illumination sources capable of a pitch distance twice the pitch distance of the parallel route tracks (206). The first interconnect pattern (208) includes a first lead pattern (212) which extends to a first point. The second interconnect pattern (220) includes a second lead pattern (224) which is parallel to and immediately adjacent to the first lead pattern (212). The third interconnect pattern (23) includes a third lead pattern (234) which is parallel to and immediately adjacent to the second lead pattern (224) and which extends to a second point (236) in the first instance of the parallel route tracks, laterally separated from the first point (214) by a distance less than one and one-half times a space between adjacent patterns in the parallel route tracks.
PCT/US2012/027554 2011-03-02 2012-03-02 Hybrid pitch-split pattern-split litrography process WO2012119105A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2013556653A JP6134652B2 (en) 2011-03-02 2012-03-02 Hybrid pitch division pattern division lithography process

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
US201161448437P 2011-03-02 2011-03-02
US201161448451P 2011-03-02 2011-03-02
US201161448423P 2011-03-02 2011-03-02
US201161448447P 2011-03-02 2011-03-02
US61/448,437 2011-03-02
US61/448,423 2011-03-02
US61/448,447 2011-03-02
US61/448,451 2011-03-02
US13/410,145 2012-03-01
US13/410,145 US8372743B2 (en) 2011-03-02 2012-03-01 Hybrid pitch-split pattern-split lithography process

Publications (2)

Publication Number Publication Date
WO2012119105A2 WO2012119105A2 (en) 2012-09-07
WO2012119105A3 true WO2012119105A3 (en) 2012-11-15

Family

ID=46758517

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/US2012/027554 WO2012119105A2 (en) 2011-03-02 2012-03-02 Hybrid pitch-split pattern-split litrography process
PCT/US2012/027534 WO2012119098A2 (en) 2011-03-02 2012-03-02 Pattern-split decomposition strategy for double-patterned lithography process

Family Applications After (1)

Application Number Title Priority Date Filing Date
PCT/US2012/027534 WO2012119098A2 (en) 2011-03-02 2012-03-02 Pattern-split decomposition strategy for double-patterned lithography process

Country Status (2)

Country Link
JP (2) JP6134652B2 (en)
WO (2) WO2012119105A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9583609B2 (en) * 2013-03-25 2017-02-28 Texas Instruments Incorporated MOS transistor structure and method of forming the structure with vertically and horizontally-elongated metal contacts
JP6805414B2 (en) * 2016-11-16 2020-12-23 東京エレクトロン株式会社 Sub-resolution substrate patterning method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5561317A (en) * 1990-08-24 1996-10-01 Canon Kabushiki Kaisha Method of manufacturing semiconductor devices
US20050212096A1 (en) * 2002-09-20 2005-09-29 Tetsuya Itano Manufacturing methods of semiconductor device and solid state image pickup device
US20080020326A1 (en) * 2006-07-21 2008-01-24 Hynix Semiconductor Inc. Pattern Decomposition Method For Double Exposure
US20100159404A1 (en) * 2008-12-12 2010-06-24 Shin-Etsu Chemical Co., Ltd. Patterning process

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3050210B2 (en) * 1998-09-24 2000-06-12 株式会社ニコン Exposure bubble and device manufacturing method using the same
CN1908812B (en) * 2005-04-12 2012-02-22 Asml蒙片工具有限公司 A method, program product and apparatus for performing double exposure lithography
US7824842B2 (en) * 2005-10-05 2010-11-02 Asml Netherlands B.V. Method of patterning a positive tone resist layer overlaying a lithographic substrate
EP2267530A1 (en) * 2006-04-06 2010-12-29 ASML MaskTools B.V. Method and apparatus for performing dark field double dipole lithography
JP2007294500A (en) * 2006-04-21 2007-11-08 Nec Electronics Corp Semiconductor device and manufacturing method thereof
JP2006303541A (en) * 2006-07-28 2006-11-02 Renesas Technology Corp Method for manufacturing semiconductor integrated circuit device
JP4945367B2 (en) * 2006-08-14 2012-06-06 エーエスエムエル マスクツールズ ビー．ブイ． Apparatus and method for separating a circuit pattern into a plurality of circuit patterns
JP2008071838A (en) * 2006-09-12 2008-03-27 Nec Electronics Corp Method for manufacturing semiconductor device
JP5032948B2 (en) * 2006-11-14 2012-09-26 エーエスエムエル マスクツールズ ビー．ブイ． Method, program and apparatus for performing pattern decomposition used in the DPT process
JP2008311502A (en) * 2007-06-15 2008-12-25 Toshiba Corp Pattern forming method
KR101532012B1 (en) * 2008-12-24 2015-06-30 삼성전자주식회사 Semiconductor device and method of forming patterns for semiconductor device
JP5235719B2 (en) * 2009-02-27 2013-07-10 株式会社日立ハイテクノロジーズ Pattern measuring device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5561317A (en) * 1990-08-24 1996-10-01 Canon Kabushiki Kaisha Method of manufacturing semiconductor devices
US20050212096A1 (en) * 2002-09-20 2005-09-29 Tetsuya Itano Manufacturing methods of semiconductor device and solid state image pickup device
US20080020326A1 (en) * 2006-07-21 2008-01-24 Hynix Semiconductor Inc. Pattern Decomposition Method For Double Exposure
US20100159404A1 (en) * 2008-12-12 2010-06-24 Shin-Etsu Chemical Co., Ltd. Patterning process

Also Published As

Publication number Publication date
WO2012119105A2 (en) 2012-09-07
WO2012119098A3 (en) 2012-11-08
WO2012119098A2 (en) 2012-09-07
JP2014510403A (en) 2014-04-24
JP6134652B2 (en) 2017-05-24
JP2014509785A (en) 2014-04-21
JP6140616B2 (en) 2017-05-31

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