JP6114577B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP6114577B2
JP6114577B2 JP2013044393A JP2013044393A JP6114577B2 JP 6114577 B2 JP6114577 B2 JP 6114577B2 JP 2013044393 A JP2013044393 A JP 2013044393A JP 2013044393 A JP2013044393 A JP 2013044393A JP 6114577 B2 JP6114577 B2 JP 6114577B2
Authority
JP
Japan
Prior art keywords
wiring
layer
wiring layer
wirings
lands
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2013044393A
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English (en)
Japanese (ja)
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JP2014175356A (ja
JP2014175356A5 (enExample
Inventor
和之 中川
和之 中川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2013044393A priority Critical patent/JP6114577B2/ja
Priority to US14/196,736 priority patent/US9330992B2/en
Publication of JP2014175356A publication Critical patent/JP2014175356A/ja
Publication of JP2014175356A5 publication Critical patent/JP2014175356A5/ja
Application granted granted Critical
Publication of JP6114577B2 publication Critical patent/JP6114577B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H10W70/60—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H05K1/0251—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance related to vias or transitions between vias and transmission lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H10W70/65—
    • H10W70/685—
    • H10W72/00—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0245—Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H05K1/0253—Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/09309—Core having two or more power planes; Capacitive laminate of two power planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09718—Clearance holes
    • H10W40/22—
    • H10W72/07354—
    • H10W72/252—
    • H10W72/29—
    • H10W72/325—
    • H10W72/347—
    • H10W72/353—
    • H10W72/354—
    • H10W72/877—
    • H10W72/923—
    • H10W72/952—
    • H10W74/15—
    • H10W90/724—
    • H10W90/734—
    • H10W90/736—

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Geometry (AREA)
  • Electromagnetism (AREA)
JP2013044393A 2013-03-06 2013-03-06 半導体装置 Active JP6114577B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2013044393A JP6114577B2 (ja) 2013-03-06 2013-03-06 半導体装置
US14/196,736 US9330992B2 (en) 2013-03-06 2014-03-04 Wiring substrate for a semiconductor device having differential signal paths

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013044393A JP6114577B2 (ja) 2013-03-06 2013-03-06 半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2016243454A Division JP6258460B2 (ja) 2016-12-15 2016-12-15 半導体装置

Publications (3)

Publication Number Publication Date
JP2014175356A JP2014175356A (ja) 2014-09-22
JP2014175356A5 JP2014175356A5 (enExample) 2015-09-17
JP6114577B2 true JP6114577B2 (ja) 2017-04-12

Family

ID=51486860

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013044393A Active JP6114577B2 (ja) 2013-03-06 2013-03-06 半導体装置

Country Status (2)

Country Link
US (1) US9330992B2 (enExample)
JP (1) JP6114577B2 (enExample)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2775806B1 (en) * 2013-03-07 2015-03-04 Tyco Electronics Svenska Holdings AB Optical receiver and transceiver using the same
USD758372S1 (en) * 2013-03-13 2016-06-07 Nagrastar Llc Smart card interface
USD759022S1 (en) * 2013-03-13 2016-06-14 Nagrastar Llc Smart card interface
JP5967071B2 (ja) * 2013-12-26 2016-08-10 株式会社デンソー 電子制御装置、および、これを用いた電動パワーステアリング装置
JP2015170770A (ja) * 2014-03-07 2015-09-28 イビデン株式会社 プリント配線板
US9589946B2 (en) * 2015-04-28 2017-03-07 Kabushiki Kaisha Toshiba Chip with a bump connected to a plurality of wirings
USD864968S1 (en) 2015-04-30 2019-10-29 Echostar Technologies L.L.C. Smart card interface
US10276519B2 (en) 2015-06-02 2019-04-30 Sarcina Technology LLC Package substrate differential impedance optimization for 25 to 60 Gbps and beyond
US10410984B1 (en) 2015-06-02 2019-09-10 Sarcina Technology LLC Package substrate differential impedance optimization for 25 to 60 GBPS and beyond
US9666544B2 (en) 2015-06-02 2017-05-30 Sarcina Technology LLC Package substrate differential impedance optimization for 25 GBPS and beyond
JP6534312B2 (ja) * 2015-07-31 2019-06-26 ルネサスエレクトロニクス株式会社 半導体装置
US9974174B1 (en) * 2016-10-26 2018-05-15 Nxp Usa, Inc. Package to board interconnect structure with built-in reference plane structure
JP2019009319A (ja) 2017-06-26 2019-01-17 ルネサスエレクトロニクス株式会社 半導体装置
JP6867268B2 (ja) * 2017-10-13 2021-04-28 ルネサスエレクトロニクス株式会社 半導体装置
JP6853774B2 (ja) * 2017-12-21 2021-03-31 ルネサスエレクトロニクス株式会社 半導体装置
JP7001530B2 (ja) * 2018-04-16 2022-01-19 ルネサスエレクトロニクス株式会社 半導体装置
CN111508901B (zh) * 2019-10-01 2022-01-25 威锋电子股份有限公司 集成电路芯片、封装基板及电子总成
US11342307B2 (en) * 2019-10-14 2022-05-24 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof
JP2021085709A (ja) * 2019-11-26 2021-06-03 日本電気株式会社 電子回路装置
US20220069489A1 (en) * 2020-08-28 2022-03-03 Unimicron Technology Corp. Circuit board structure and manufacturing method thereof
JP2024041144A (ja) * 2022-09-14 2024-03-27 京セラドキュメントソリューションズ株式会社 信号処理基板、画像形成装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6587008B2 (en) 2000-09-22 2003-07-01 Kyocera Corporation Piezoelectric oscillator and a method for manufacturing the same
KR100917081B1 (ko) * 2001-03-14 2009-09-15 이비덴 가부시키가이샤 다층 프린트 배선판
JP2003168864A (ja) * 2001-09-20 2003-06-13 Kyocera Corp 多層配線基板
JP2003124633A (ja) * 2001-10-19 2003-04-25 Kyocera Corp 多層配線基板
JP3872413B2 (ja) * 2002-11-05 2007-01-24 三菱電機株式会社 半導体装置
CN101887880B (zh) * 2004-02-04 2012-11-14 揖斐电株式会社 多层印刷电路板
JP4606776B2 (ja) 2004-05-28 2011-01-05 ルネサスエレクトロニクス株式会社 半導体装置
JP2006049645A (ja) * 2004-08-05 2006-02-16 Ngk Spark Plug Co Ltd 配線基板
JP2010219498A (ja) 2009-02-20 2010-09-30 Elpida Memory Inc 半導体装置
WO2011018938A1 (ja) * 2009-08-12 2011-02-17 日本電気株式会社 多層プリント配線板
JP2011138846A (ja) * 2009-12-27 2011-07-14 Kyocer Slc Technologies Corp 配線基板

Also Published As

Publication number Publication date
JP2014175356A (ja) 2014-09-22
US20140252612A1 (en) 2014-09-11
US9330992B2 (en) 2016-05-03

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