JP6867268B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6867268B2 JP6867268B2 JP2017199633A JP2017199633A JP6867268B2 JP 6867268 B2 JP6867268 B2 JP 6867268B2 JP 2017199633 A JP2017199633 A JP 2017199633A JP 2017199633 A JP2017199633 A JP 2017199633A JP 6867268 B2 JP6867268 B2 JP 6867268B2
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Description
本願において、実施の態様の記載は、必要に応じて、便宜上複数のセクション等に分けて記載するが、特にそうでない旨明示した場合を除き、これらは相互に独立別個のものではなく、記載の前後を問わず、単一の例の各部分、一方が他方の一部詳細または一部または全部の変形例等である。また、原則として、同様の部分は繰り返しの説明を省略する。また、実施の態様における各構成要素は、特にそうでない旨明示した場合、理論的にその数に限定される場合および文脈から明らかにそうでない場合を除き、必須のものではない。
まず、本実施の形態の半導体装置PKG1の概要構成について、図1〜図4を用いて説明する。図1は本実施の形態の半導体装置の斜視図、図2は、図1に示す半導体装置の下面図である。また、図3は、図1に示す半導体装置の上面図である。また、図4は図1のA−A線に沿った断面図である。なお、図1〜図4では、見易さのため、端子数を少なくして示している。また、図4では、見易さのため、図2に示す例よりも外部端子30の数を少なくして示している。図示は省略するが、端子(端子2PD、ランド2LD、外部端子30)の数は、図1〜図4に示す態様以外にも種々の変形例が適用できる。
次に、図4に示す半導体チップが備える回路構成例について説明する。図5は、図4に示す半導体チップが有する回路構成例を模式的に示す説明図である。また、図6は、図1に示す半導体チップの表面(電極配置面)の平面図である。図6は平面図であるが、複数の電極1PDv、複数の電極1PDg、および複数の電極1PDsのそれぞれを識別するため、ドットパターンやハッチングを付している。図6において、円形で示される複数の電極1PDのうち、電極1PDsは、白抜きで示され、電極1PDvは、ドットパターンで示され、電極1PDgはハッチングで示される。
以下、図4に示す配線基板20が有する各配線層における配線レイアウトについて図面を用いて詳細に説明する。図7は、図3に示す配線基板の上面において、半導体チップおよびアンダフィル樹脂を取り除いた状態を示す平面図である。図8は、図7に示す配線基板において、最上層の絶縁膜を取り除き、第1層目の配線層のレイアウトの例を示す平面図である。図7および図8では、図7に示すチップ搭載領域と重畳する領域を拡大して示している。図9は、図8の中央部分を拡大した拡大平面図である。図9では、図8の拡大図の一部分をさらに拡大している。図10は、図7に示す配線基板において、第2層目の配線層のレイアウトの例を示す平面図である。図11は、図10に示す配線層のうち、図9に示す平面と重畳する中央部分を拡大した拡大平面図である。図7〜図11のそれぞれは平面図であるが、信号伝送経路と、電源電位の供給経路と、基準電位の供給経路と、をそれぞれ識別するため、図6と同様の模様を付している。すなわち、図7〜図11において、信号伝送経路は白抜きで示され、電源電位の供給経路は、ドットパターンで示され、基準電位の供給経路はハッチングで示される。また、図9および図11において、配線基板20が有する端子2PDの位置(言い換えれば、図6に示す半導体チップ10の電極1PDと重畳する位置)は、点線で示している。また、図9および図11において、配線2wvの直下にビア配線2vvがある位置は、周辺よりも濃いドットパターンで示している。また、図9および図11において、配線2wgの直下にビア配線2vgがある位置は、周辺とは反対向きのハッチングで示している。また、図11では、図9に示す配線2wvおよび配線2wgの輪郭を点線で示している。
例えば、図4に示す半導体装置PKG1では、配線基板の構造例として、6層の配線層を有する配線基板20を取り上げて説明した。しかし、配線層の数は、6層には限定されず、種々の変形例が適用可能である。図22は、図4に対する変形例である半導体装置の断面図である。また、図23は、図22に示す配線基板において、第1層目の配線層のレイアウトの例を示す拡大平面図である。また、図24は、図23に示す配線基板において、第2層目の配線層のレイアウトの例を示す拡大平面図である。
また例えば、図4では、半導体チップ10と配線基板20とが突起電極SBを介して電気的に接続される実施態様について説明した。上記した技術は、半導体チップ10と配線基板20とがワイヤを介して電気的に接続されている配線装置に適用することを排除するものではない。ただし、配線基板20と半導体チップ10とを電気的に接続する導電経路のインピーダンスを低減する観点からは、上記したようにフリップチップ接続方式を適用することが特に好ましい。また、配線基板20内における電源電位の供給経路および基準電位の供給経路を短くする観点からも、フリップチップ接続方式を適用することが好ましい。
また、例えば、上記の通り種々の変形例について説明したが、上記で説明した各変形例同士を組み合わせて適用することができる。
2Ca 上面
2Cb 下面
2CR 絶縁層(コア層、コア材、コア絶縁層)
2e,2e1 絶縁膜
2eH 開口部
2LD ランド(端子、外部端子、電極、外部電極)
2PD,2PDg,2PDs,2PDv 端子(端子部、パッド、半導体チップ接続用端子)
2Pg1,2Pg2,2Pg3,2Pg4,2Pg5,2PgA,2PgB,2Pv1,2Pv2,2Pv3,2Pv4,2Pv5,2PvA,2PvB 導体パターン
2PL 導体プレーン
2Pvc 連結部
2TW,2TWg,2TWs,2TWv スルーホール配線(層間導電路)
2v,2vg,2vg2,2vg3,2vg4,2vs,2vv,2vv2,2vv3,2vv4 ビア配線(ビア、層間導電路)
2we1 端部(第1端部)
2we2 端部(第2端部)
2w,2wg,2wv,2wgA,2wgB,2ws,2wv,2wvA,2wvB 配線(導体パターン、配線パターン)
2wg1,2wv1 主配線部
2wg2,2wv2 副配線部
10 半導体チップ
10b 裏面(主面、下面)
10r チップ搭載領域
10s 側面
10t 表面(主面、上面)
11 入出力回路
12 コア回路
20,21 配線基板
20b 下面(面、主面、実装面)
20s 側面
20t 上面(面、主面、チップ搭載面)
30 外部端子(半田ボール、半田材、端子、電極、外部電極)
40 アンダフィル樹脂(絶縁性樹脂)
PKG1,PKG2 半導体装置
SB,SBg,SBv 突起電極
SIG 電気信号
VD 電源電位
VG 基準電位
WL1,WL2,WL3,WL4,WL5,WL6 配線層
Claims (18)
- 第1表面、前記第1表面の反対側の第1裏面、および前記第1表面に配列される複数の電極を有する半導体チップと、
前記半導体チップが搭載される第1主面、第1主面の反対側の第2主面、前記第1主面と前記第2主面との間にある第1配線層、および前記第1配線層と前記第2主面との間にあり、かつ、前記第1主面に交差する方向の断面視において前記第1配線層の隣にある第2配線層を有する配線基板と、
を有し、
前記第1配線層は、
平面視において、第1方向に延びる第1主配線部、および前記第1方向と交差する第2方向に延び、かつ、前記第1主配線部と交差する複数の第1副配線部を有し、かつ、第1電位が供給される第1配線と、
平面視において、前記第1方向に延びる第2主配線部、および前記第2方向に延び、かつ、前記第2主配線部と交差する複数の第2副配線部を有し、かつ、前記第1電位とは異なる第2電位が供給される第2配線と、
を有し、
前記第1配線の前記複数の第1副配線部、および前記第2配線の前記複数の第2副配線部のそれぞれは、
第1端部、および前記第2方向において、前記第1主配線部または前記第2主配線部を介して前記第1端部の反対側にある第2端部を有し、
かつ、前記第1主配線部と前記第2主配線部との間において、前記第1方向に沿って交互に配列され、
前記第2配線層は、
前記第2配線の前記第2主配線部、および前記第1配線の前記複数の第1副配線部の前記第1端部と重畳し、かつ、前記第1方向に延びる第1導体パターンと、
前記第1配線の前記第1主配線部、および前記第2配線の前記複数の第2副配線部の前記第2端部と重畳する第2導体パターンと、
を有し、
前記複数の第1副配線部の前記第1端部は、複数の第1ビアを介して前記第1導体パターンと電気的に接続され、
前記複数の第2副配線部の前記第2端部は、複数の第2ビアを介して前記第2導体パターンと電気的に接続される、半導体装置。 - 請求項1において、
前記半導体チップの前記第1表面は、前記配線基板の前記第1主面と対向し、
前記半導体チップの前記複数の電極は、
前記配線基板の前記第1配線に電気的に接続される複数の第1電極と、
前記配線基板の前記第2配線に電気的に接続される複数の第2電極と、
を有し、
前記配線基板は、前記半導体チップの前記複数の第1電極と対向し、かつ、電気的に接続される複数の第1端子と、前記半導体チップの前記複数の第2電極と対向し、かつ、電気的に接続される複数の第2端子と、を有する、半導体装置。 - 請求項2において、
前記配線基板は、
前記第1配線層を覆い、かつ複数の開口部を備える第1絶縁膜を有し、
前記第1配線は、前記第1絶縁膜が備える前記複数の開口部において前記第1絶縁膜から露出する前記複数の第1端子を有し、
前記第2配線は、前記第1絶縁膜が備える前記複数の開口部において前記第1絶縁膜から露出する前記複数の第2端子を有し、
前記半導体チップの前記複数の第1電極と前記複数の第1端子とは、第1突起電極を介してそれぞれ接続され、
前記半導体チップの前記複数の第2電極と前記複数の第2端子とは、第2突起電極を介してそれぞれ接続される、半導体装置。 - 請求項3において、
前記複数の第1端子は、前記複数の第1副配線部の前記第1端部および前記第2端部にある複数の第3端子を含み、
前記複数の第2端子は、前記複数の第2副配線部の前記第1端部および前記第2端部にある複数の第4端子を含む、半導体装置。 - 請求項4において、
前記複数の第3端子のそれぞれは、前記複数の第1ビアのそれぞれと重畳し、
前記複数の第4端子のそれぞれは、前記複数の第2ビアのそれぞれと重畳する、半導体装置。 - 請求項4において、
前記複数の第1端子は、前記第1主配線部にある第5端子を含み、
前記複数の第2端子は、前記第2主配線部にある第6端子を含む、半導体装置。 - 請求項6において、
前記第5端子は、前記複数の第1ビアと重畳せず、
前記第6端子は、前記複数の第2ビアと重畳しない、半導体装置。 - 請求項1において、
前記第2配線層は、
前記第1配線の前記複数の第1副配線部の前記第2端部と重畳し、かつ、前記第1方向に延びる第3導体パターンを有し、
平面視において、前記第2導体パターンは、前記第1導体パターンと前記第3導体パターンとの間にあり、
前記複数の第1副配線部の前記第2端部は、前記複数の第1ビアを介して前記第3導体パターンと電気的に接続される、半導体装置。 - 請求項8において、
前記第2配線層は、前記第2方向において、前記第1導体パターンと前記第3導体パターンとの間に配置され、かつ、前記第1方向に沿って一列で配列される複数の前記第2導体パターンを有し、
前記第1導体パターンと前記第3導体パターンとは、前記複数の第2導体パターンの間にある連結部を介して電気的に接続される、半導体装置。 - 請求項8において、
前記第2配線層は、前記第2配線の前記複数の第2副配線部の前記第1端部と重畳する第4導体パターンを有し、
平面視において、前記第1導体パターンは、前記第2導体パターンと前記第4導体パターンとの間にあり、
前記複数の第2副配線部の前記第1端部は、前記複数の第2ビアを介して前記第4導体パターンと電気的に接続される、半導体装置。 - 請求項10において、
前記第2配線層は、前記第2方向において、前記第1導体パターンと前記第3導体パターンとの間に配置され、かつ、前記第1方向に沿って一列で配列される複数の前記第2導体パターンを有し、
前記複数の第2導体パターンは、前記第1配線層の前記第2配線を介して互いに電気的に接続されている、半導体装置。 - 請求項1において、
前記配線基板は、前記第2配線層と前記第2主面との間にあり、かつ、前記第1主面に交差する方向の断面視において前記第2配線層の隣にある第3配線層を有し、
前記第3配線層は、
前記第1導体パターンと重畳し、かつ、複数の第3ビアを介して前記第1導体パターンと電気的に接続され、かつ、前記第1方向に延びる第3導体パターンと、
前記第2導体パターンと重畳し、かつ、複数の第4ビアを介して前記第2導体パターンと電気的に接続され、かつ、前記第1方向に延びる第4導体パターンと、
を有する、半導体装置。 - 請求項12において、
前記配線基板は、
前記第3配線層と前記第2主面との間にある第4配線層と、
前記第3配線層と前記第4配線層とを電気的に接続する複数のスルーホール配線と、
を有し、
前記複数のスルーホール配線には、前記第3配線層において前記第3導体パターンに接続される複数の第1スルーホール配線と、前記第3配線層において前記第4導体パターンに接続される複数の第2スルーホール配線と、が含まれる、半導体装置。 - 請求項13において、
前記半導体チップの前記複数の電極の配列間隔は、前記配線基板の前記複数のスルーホール配線の配列間隔より小さい、半導体装置。 - 請求項1において、
前記配線基板の前記第1配線層は、複数の前記第1配線および複数の前記第2配線を有し、
平面視において、前記第2方向に沿って前記複数の第1配線と前記複数の第2配線とが交互に配列されている、半導体装置。 - 請求項1において、
前記第1配線層は、平面視において、前記第1方向に延びる第3主配線部、および前記第2方向に延び、かつ、前記第3主配線部と交差する複数の第3副配線部を有し、かつ、前記第2電位が供給される第3配線、を有し、
前記第1配線は、前記第2方向において、前記第2配線と前記第3配線との間に配置され、
前記第3配線の前記複数の第3副配線部のそれぞれは、前記第1端部、および前記第2方向において、前記第3主配線部を介して前記第1端部の反対側にある前記第2端部を有し、
前記複数の第1副配線部と前記複数の第3副配線部とは、前記第1主配線部と前記第3主配線部との間において、前記第1方向に沿って交互に配列され、
前記第2配線層は、前記第3配線の前記第3主配線部、および前記第1配線の前記複数の第1副配線部の前記第2端部と重畳する第3導体パターンを有し、
前記複数の第1副配線部の前記第2端部は、前記複数の第1ビアを介して前記第3導体パターンと電気的に接続され、
前記複数の第3副配線部の前記第1端部は、前記複数の第2ビアを介して前記第2導体パターンと電気的に接続される、半導体装置。 - 請求項1において、
前記第1配線層は、平面視において、前記第1方向に延びる第4主配線部、および前記第2方向に延び、かつ、前記第4主配線部と交差する複数の第4副配線部を有し、かつ、前記第1電位が供給される第4配線、を有し、
前記第2配線は、前記第2方向において、前記第1配線と前記第4配線との間に配置され、
前記第4配線の前記複数の第4副配線部のそれぞれは、前記第1端部、および前記第2方向において、前記第4主配線部を介して前記第1端部の反対側にある前記第2端部を有し、
前記複数の第2副配線部と前記複数の第4副配線部とは、前記第2主配線部と前記第4主配線部との間において、前記第1方向に沿って交互に配列され、
前記第2配線層は、前記第4配線の前記第4主配線部、および前記第2配線の前記複数の第2副配線部の前記第1端部と重畳する第4導体パターンを有し、
前記複数の第2副配線部の前記第1端部は、前記複数の第2ビアを介して前記第4導体パターンと電気的に接続され、
前記複数の第4副配線部の前記第1端部は、戦記複数の第1ビアを介して前記第1導体パターンと電気的に接続される、半導体装置。 - 請求項1において、
前記半導体チップは、前記第1電位と前記第2電位との電位差により駆動される回路を有し、
前記第2電位は接地電位であり、前記第1電位は前記接地電位と異なる電源電位である、半導体装置。
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