JP6107362B2 - 半導体装置の製造方法及び半導体装置 - Google Patents
半導体装置の製造方法及び半導体装置 Download PDFInfo
- Publication number
- JP6107362B2 JP6107362B2 JP2013087899A JP2013087899A JP6107362B2 JP 6107362 B2 JP6107362 B2 JP 6107362B2 JP 2013087899 A JP2013087899 A JP 2013087899A JP 2013087899 A JP2013087899 A JP 2013087899A JP 6107362 B2 JP6107362 B2 JP 6107362B2
- Authority
- JP
- Japan
- Prior art keywords
- mold
- terminals
- terminal
- resin case
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 63
- 238000004519 manufacturing process Methods 0.000 title claims description 24
- 229920005989 resin Polymers 0.000 claims description 149
- 239000011347 resin Substances 0.000 claims description 149
- 238000000465 moulding Methods 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 16
- 239000004734 Polyphenylene sulfide Substances 0.000 claims description 9
- 229920000069 polyphenylene sulfide Polymers 0.000 claims description 9
- 229920000122 acrylonitrile butadiene styrene Polymers 0.000 claims description 5
- -1 polybutylene terephthalate Polymers 0.000 claims description 5
- 229920001707 polybutylene terephthalate Polymers 0.000 claims description 5
- XECAHXYUAAWDEL-UHFFFAOYSA-N acrylonitrile butadiene styrene Chemical compound C=CC=C.C=CC#N.C=CC1=CC=CC=C1 XECAHXYUAAWDEL-UHFFFAOYSA-N 0.000 claims description 3
- 239000004676 acrylonitrile butadiene styrene Substances 0.000 claims description 3
- 229920006122 polyamide resin Polymers 0.000 claims description 3
- 230000004048 modification Effects 0.000 description 17
- 238000012986 modification Methods 0.000 description 17
- 239000004020 conductor Substances 0.000 description 14
- 239000000758 substrate Substances 0.000 description 9
- 239000000853 adhesive Substances 0.000 description 8
- 230000001070 adhesive effect Effects 0.000 description 8
- 230000017525 heat dissipation Effects 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 238000007789 sealing Methods 0.000 description 6
- 238000005452 bending Methods 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 3
- 238000006073 displacement reaction Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 229910001369 Brass Inorganic materials 0.000 description 1
- 229910000906 Bronze Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- JRBRVDCKNXZZGH-UHFFFAOYSA-N alumane;copper Chemical compound [AlH3].[Cu] JRBRVDCKNXZZGH-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000010951 brass Substances 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
銅板等の導電材の薄板を、打ち抜き加工及び曲げ加工することにより、樹脂ケースの一つの側壁部に対応する数及び位置になるように端子がタイバーで接続されている端子部材を、樹脂ケースの側壁ごとに用意する。この端子部材を、樹脂ケースを成型する金型内に、樹脂ケースの側壁のそれぞれに対応させてセットし、この金型に原料樹脂、例えばPPS(ポリフェニレンサルファイド:Polyphenylene Sulfide)樹脂等を注入し、固化させることにより、端子を樹脂ケースと一体的にインサート成型する。成型後に、タイバーを切除する。
前記樹脂ケースを成型するための金型に、前記複数の端子のそれぞれを所定の位置に固定する突起を、前記金型に保持される端子の脚部の根元近傍に対応する位置に設けておき、
上型及び下型を備える該金型に複数の端子のそれぞれを、該突起に適合させて保持するとともに、前記上型及び前記下型により、前記端子の脚部の先端部近傍を挟持し、
該金型に樹脂を注入して、複数の端子と樹脂ケースとを一体的に成型する。
前記複数の端子と樹脂ケースとが金型を用いて一体的に成型されてなり、かつ、
前記樹脂ケースの、前記複数の端子の脚部近傍に、該複数の端子のそれぞれを前記金型の所定の位置に固定した突起の突起跡が、前記端子の脚部の根元近傍に形成されているとともに、前記端子の脚部の先端部の表面及び裏面が、前記樹脂ケースから露出している。
本発明の一実施形態の半導体装置10を図1に要部の断面図で示す。図1において半導体装置10は、半導体チップ11が、絶縁回路基板12上に搭載されている。半導体チップ11は、例えばIGBT(絶縁ゲートバイポーラトランジスタ;Insulated Gate Bipolar Transistor)やFWD(フリーホイーリングダイオード;Free Wheeling Diode)とすることができる。
図6に、樹脂ケース15を成型するための金型の変形例を部分断面図で示す。図6において、図5と同一部材については同一符号を付し、以下では重複する説明を省略する。図6の金型20Aの、図5の金型20と相違する点は、図5における金型20の上型21に設けられた突起21aと同じ位置に設けられる突起21bの、下型22に向かう方向の長さが、端子17の脚部17aの厚さと同じ程度である点である。そのため、図6(c)のA−A線断面図で示す図6(a)では、端子17の手前に位置する突起21bが端子17の脚部17aの厚さと同じ長さで図示されていて、図6(c)では端子17の脚部17aに隣り合う突起21bが端子17の脚部17aの厚さと同じ長さで図示されている。図6の金型20Aにおいて、上型21Dの突起21bの長さが端子17の脚部17aの厚さと同じであっても、図5を用いて前に説明した金型20の効果を全て具備することができる。むしろ上型21Dの突起21bの長さが端子17の脚部17aの厚さと同じ程度に短いほうが、突起21bの折れ等の破損を招くおそれが少なく、好ましい場合もある。
例えば、上記の例では同一形状の端子17を用い、突起21aがほぼ等間隔で設けられた金型20によりインサート成型する製造方法について説明したが、幅や厚みの異なる端子をそれぞれ用意し、これらの端子に適合するような間隔で、位置決めのための突起を複数設けた金型により成型してもよい。主端子と制御端子として異なる形状の端子を用い、それぞれの端子を所定の位置に保持するための突起を設けた金型により成型すれば、異なる形状の端子を備え、異なる端子配列に対応できる半導体装置の製造方法を低コストで提供できる。
11 半導体チップ
12 絶縁回路基板
13 半田
14 放熱用基板
15、15G、35、45、55 樹脂ケース
16 接着剤
17 端子
17a 脚部
18 ボンディングワイヤ
19 封止樹脂
20、20A、24、27 金型
21、21D、25 上型
22、28 下型
23、26、29 キャビティ
21a、25a 突起
Claims (7)
- 少なくとも一つの半導体素子が搭載された絶縁回路基板を、脚部を有する複数の端子が設けられた樹脂ケースに取り付けた半導体装置の製造方法であって、
前記樹脂ケースを成型するための金型に、前記複数の端子のそれぞれを所定の位置に固定する突起を、前記金型に保持される端子の脚部の根元近傍に対応する位置に設けておき、
上型及び下型を備える該金型に複数の端子のそれぞれを、該突起に適合させて保持するとともに、前記上型及び前記下型により、前記端子の脚部の先端部近傍を挟持し、
該金型に樹脂を注入して、複数の端子と樹脂ケースとを一体的に成型する、
ことを特徴とする半導体装置の製造方法。 - 前記金型が上型と下型とを備え、前記突起を、上型又は下型のうちの、端子を取り付ける側の金型に設けた請求項1記載の半導体装置の製造方法。
- 前記突起を、前記端子の脚部の根元近傍両側に設ける請求項1記載の半導体装置の製造方法。
- 複数の端子を、一度に金型に保持する請求項1〜3のいずれか1項に記載の半導体装置の製造方法。
- 少なくとも一つの半導体素子が搭載された絶縁回路基板と、脚部を有する複数の端子が設けられた樹脂ケースと、を備える半導体装置において、
前記複数の端子と樹脂ケースとが金型を用いて一体的に成型されてなり、かつ、
前記樹脂ケースの、前記複数の端子の脚部近傍に、該複数の端子のそれぞれを前記金型の所定の位置に固定した突起の突起跡が、前記端子の脚部の根元近傍に形成されているとともに、前記端子の脚部の先端部の表面及び裏面が、前記樹脂ケースから露出していることを特徴とする半導体装置。 - 前記端子の脚部の根元近傍における前記樹脂ケースの側壁部の厚さが、他の側壁部の部分よりも厚い請求項5記載の半導体装置。
- 前記樹脂ケースがポリフェニレンサルファイド樹脂、ポリブチレンテレフタレート樹脂、ポリアミド樹脂及びアクリロニトリルブタジエンスチレン樹脂から選ばれる1種の樹脂よりなる請求項5又は6記載の半導体装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013087899A JP6107362B2 (ja) | 2013-04-18 | 2013-04-18 | 半導体装置の製造方法及び半導体装置 |
CN201410142784.1A CN104167370B (zh) | 2013-04-18 | 2014-04-10 | 半导体装置制造方法及半导体装置 |
US14/251,036 US9070696B2 (en) | 2013-04-18 | 2014-04-11 | Semiconductor device manufacturing method and semiconductor device |
EP14164833.7A EP2793256B1 (en) | 2013-04-18 | 2014-04-16 | Semiconductor device manufacturing method |
US14/715,018 US9466509B2 (en) | 2013-04-18 | 2015-05-18 | Semiconductor device manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013087899A JP6107362B2 (ja) | 2013-04-18 | 2013-04-18 | 半導体装置の製造方法及び半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014212218A JP2014212218A (ja) | 2014-11-13 |
JP6107362B2 true JP6107362B2 (ja) | 2017-04-05 |
Family
ID=50732781
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013087899A Active JP6107362B2 (ja) | 2013-04-18 | 2013-04-18 | 半導体装置の製造方法及び半導体装置 |
Country Status (4)
Country | Link |
---|---|
US (2) | US9070696B2 (ja) |
EP (1) | EP2793256B1 (ja) |
JP (1) | JP6107362B2 (ja) |
CN (1) | CN104167370B (ja) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6299120B2 (ja) * | 2013-09-05 | 2018-03-28 | 富士電機株式会社 | 半導体モジュール |
JP6451257B2 (ja) * | 2014-11-21 | 2019-01-16 | 富士電機株式会社 | 半導体装置 |
KR102425694B1 (ko) * | 2015-03-17 | 2022-07-27 | 주식회사 솔루엠 | 파워 모듈 패키지 |
JP6547354B2 (ja) * | 2015-03-20 | 2019-07-24 | 富士電機株式会社 | 半導体モジュールおよび樹脂ケース |
JP6645134B2 (ja) * | 2015-11-16 | 2020-02-12 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
JP6984127B2 (ja) * | 2016-12-28 | 2021-12-17 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
JP6988161B2 (ja) * | 2017-05-17 | 2022-01-05 | 富士電機株式会社 | パワー半導体モジュールおよびパワー半導体装置 |
CN111148338A (zh) * | 2018-11-01 | 2020-05-12 | 邱昱维 | 在布局有电路的陶瓷基板上成形环绕壁的方法及该基板 |
JP7318238B2 (ja) * | 2019-03-11 | 2023-08-01 | 富士電機株式会社 | 半導体装置 |
CN111916361A (zh) * | 2019-05-10 | 2020-11-10 | 中芯长电半导体(江阴)有限公司 | 一种塑封模具及塑封方法 |
JP7313302B2 (ja) * | 2020-03-18 | 2023-07-24 | 三菱電機株式会社 | 半導体装置および半導体装置の製造方法 |
JP7353255B2 (ja) * | 2020-10-30 | 2023-09-29 | 三菱電機株式会社 | 半導体装置用の筐体の製造方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2705368B2 (ja) * | 1991-05-31 | 1998-01-28 | 株式会社デンソー | 電子装置 |
JP3466329B2 (ja) | 1995-06-16 | 2003-11-10 | 三菱電機株式会社 | 半導体パワーモジュール |
CN1248376C (zh) * | 2001-11-08 | 2006-03-29 | 莫列斯公司 | 电连接器的制造方法及其制品 |
JP4007143B2 (ja) * | 2002-10-09 | 2007-11-14 | 日産自動車株式会社 | 電子部品、電子部品の製造方法及び製造装置 |
JP4141789B2 (ja) * | 2002-10-11 | 2008-08-27 | 三菱電機株式会社 | 電力用半導体装置 |
DE102004054597B4 (de) * | 2004-11-11 | 2019-07-25 | Infineon Technologies Ag | Elektronisches Bauteil und Verfahren zum Herstellen eines elektronischen Bauteils |
US7944042B2 (en) | 2007-03-08 | 2011-05-17 | Fuji Electric Device Technology Co., Ltd. | Semiconductor device and method of manufacturing same |
JP4985116B2 (ja) * | 2007-03-08 | 2012-07-25 | 富士電機株式会社 | 半導体装置およびその製造方法 |
JP4858336B2 (ja) | 2007-07-10 | 2012-01-18 | 三菱電機株式会社 | 電力用半導体装置 |
-
2013
- 2013-04-18 JP JP2013087899A patent/JP6107362B2/ja active Active
-
2014
- 2014-04-10 CN CN201410142784.1A patent/CN104167370B/zh active Active
- 2014-04-11 US US14/251,036 patent/US9070696B2/en active Active
- 2014-04-16 EP EP14164833.7A patent/EP2793256B1/en active Active
-
2015
- 2015-05-18 US US14/715,018 patent/US9466509B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US9070696B2 (en) | 2015-06-30 |
EP2793256A2 (en) | 2014-10-22 |
US20140312464A1 (en) | 2014-10-23 |
CN104167370A (zh) | 2014-11-26 |
EP2793256B1 (en) | 2021-01-13 |
US20150249023A1 (en) | 2015-09-03 |
EP2793256A3 (en) | 2016-04-06 |
US9466509B2 (en) | 2016-10-11 |
CN104167370B (zh) | 2018-10-23 |
JP2014212218A (ja) | 2014-11-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6107362B2 (ja) | 半導体装置の製造方法及び半導体装置 | |
JP4242401B2 (ja) | 半導体装置 | |
EP3226292B1 (en) | Lead frame, semiconductor device, method for manufacturing lead frame, and method for manufacturing semiconductor device | |
JP5252819B2 (ja) | 半導体装置およびその製造方法 | |
US8922317B2 (en) | Coil component | |
US9806010B2 (en) | Package module and method of fabricating the same | |
JP6673012B2 (ja) | 半導体装置およびその製造方法 | |
JPWO2020129195A1 (ja) | 半導体装置、及び、半導体装置の製造方法 | |
JP6165025B2 (ja) | 半導体モジュール | |
US10586773B2 (en) | Semiconductor device | |
JP2006108306A (ja) | リードフレームおよびそれを用いた半導体パッケージ | |
JP5245880B2 (ja) | 電力用半導体モジュールとその製造方法 | |
US9559048B2 (en) | Circuit carrier and method for producing a circuit carrier | |
JP2009094189A (ja) | コネクタ付き半導体パッケージ | |
US20190013267A1 (en) | Packaged IC Component | |
JP2008098506A (ja) | コイル部品及びコイル部品の製造方法 | |
JP6625037B2 (ja) | 半導体装置および半導体装置の製造方法 | |
JP2000349219A (ja) | 引き出し端子、電力用半導体装置用ケース及び電力用半導体装置 | |
US7550827B2 (en) | Conductor frame for an electronic component and method for the production thereof | |
JP2005328009A (ja) | チップパッケージ、該チップパッケージの製造方法およびチップ実装基板 | |
JP2015037103A (ja) | 半導体装置及び半導体装置の製造方法 | |
JP2009130007A (ja) | 半導体装置及びその製造方法 | |
JP2018107326A (ja) | 回路構成体およびその製造方法 | |
US20140312997A1 (en) | Encapsulated Reed Relay | |
JP2015005687A (ja) | 樹脂パッケージとこの樹脂パッケージを用いた電子機器 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20160114 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20161024 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20161101 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20170104 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20170207 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20170220 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6107362 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |