JP7318238B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7318238B2 JP7318238B2 JP2019043891A JP2019043891A JP7318238B2 JP 7318238 B2 JP7318238 B2 JP 7318238B2 JP 2019043891 A JP2019043891 A JP 2019043891A JP 2019043891 A JP2019043891 A JP 2019043891A JP 7318238 B2 JP7318238 B2 JP 7318238B2
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- H01L2924/19107—Disposition of discrete passive components off-chip wires
Description
第1変形例では、外部接続端子16のおもて面16aの表出領域16a1のボンディングワイヤ17が接合される接合領域16a3に対応する配置面15b1の部分が段差を構成している場合について、図8を用いて説明する。図8は、第1変形例における半導体装置の外部接続端子を説明するための図である。なお、図8(A)は、外部接続端子16のおもて面16aの表出領域16a1の平面図を、図8(B)は、図8(A)の一点鎖線Y-Yにおける断面図を示している。
第2変形例では、外部接続端子16のおもて面16aの表出領域16a1の両側の配置面15b1が段差を構成している場合について、図9を用いて説明する。図9は、第2変形例における半導体装置の外部接続端子を説明するための図である。なお、図9(A)は、外部接続端子16のおもて面16aの表出領域16a1の平面図を、図9(B)は、図9(A)の一点鎖線Y-Yにおける断面図を示している。
第3変形例では、外部接続端子16の表出領域16a1の周囲のうち3辺がケース15の配置面15b1と段差が構成されている場合について、図10を用いて説明する。図10は、第3変形例における半導体装置の外部接続端子を説明するための図である。なお、図10(B)は、図10(A)における一点鎖線Y-Yにおける断面図、図10(C)は、図10(A)における一点鎖線X-Xにおける断面図をそれぞれ表している。
第4変形例では、外部接続端子16の表出領域16a1の周囲のうち4辺(全周)がケース15の配置面15b1と段差が構成されている場合について、図11を用いて説明する。図11は、第4変形例における半導体装置の外部接続端子を説明するための図である。なお、図11(B)は、図11(A)における一点鎖線Y-Yにおける断面図、図11(C)は、図11(A)における一点鎖線X-Xにおける断面図をそれぞれ表している。
第5変形例では、第1~第4変形例のようにケース15の側段差部15b3に段差を構成することに加えて、または、これらとは別に図12に示される構成を成すことができる。図12は、第5変形例における半導体装置のケースを説明するための図である。なお、図12は、図4に対応する位置の要部拡大図である。また、図12では、図4と同じ構成には同じ符号を付している。
11 半導体素子
12 セラミック回路基板
12a 絶縁板
12b 回路パターン
12c 金属板
13 放熱板
14a,14b はんだ
14c 絶縁性接着剤
15 ケース
15a 枠部
15a1 開口領域
15a2,15b2 内壁面
15b 端子配置部
15b1 配置面
15b3 側段差部
15c 端子間突起部
16 外部接続端子
16a おもて面
16a1,16b1 表出領域
16a2 バリ
16a3 接合領域
16b 裏面
16b2 ダレ面
17 ボンディングワイヤ
18 封止部材
30 打ち抜き装置
31 押圧部
31a パンチ
32 支持部
32a ダイ
160 厚板
Claims (11)
- 半導体素子と、
平板状であって、前記半導体素子と電気的に接続されるおもて面と前記おもて面の反対側の裏面とを備える外部接続端子と、
前記半導体素子を収納する開口領域に対面する内壁面を有し、前記外部接続端子を埋設する枠部と、前記内壁面から前記開口領域に突出する配置面を有し、前記おもて面の表出領域を表出し、前記裏面を埋設する端子配置部と、を備えるケースと、
前記開口領域において、前記半導体素子を封止する封止部材と、
を有し、
前記外部接続端子の前記表出領域における1組の対辺の両側の少なくとも一部において、前記配置面が前記おもて面と前記裏面との間に位置して前記おもて面に対して段差を構成する、
半導体装置。 - 段差を構成する、前記端子配置部の前記配置面から前記外部接続端子の前記おもて面までの段差高さは、前記外部接続端子の前記おもて面から前記裏面までの厚さの4分の1以上である、
請求項1に記載の半導体装置。 - 前記外部接続端子の前記表出領域は、前記半導体素子と電気的に配線接合される接合領域を含んでおり、前記対辺のうち、前記接合領域を挟むそれぞれの両側の前記配置面の側段差部が前記おもて面に対して段差を構成している、
請求項1または2に記載の半導体装置。 - 前記外部接続端子の前記表出領域は、平面視で前記対辺と前記対辺の間の辺とに隣接する前記配置面が前記おもて面に対して段差を構成している、
請求項1または2に記載の半導体装置。 - 前記外部接続端子の前記表出領域は、平面視で前記対辺と前記対辺の間の対辺とに隣接する前記配置面が前記おもて面に対して段差を構成している、
請求項1または2に記載の半導体装置。 - 前記外部接続端子は、前記裏面にダレ面を備える、
請求項1乃至5のいずれかに記載の半導体装置。 - 前記外部接続端子は、前記おもて面にバリを備える、
請求項1乃至5のいずれかに記載の半導体装置。 - 前記ケースは、ポリフェニレンサルファイド、ポリブチレンテレフタレート樹脂、ポリブチレンサクシネート樹脂、ポリアミド樹脂、アクリロニトリルブタジエンスチレン樹脂、または、ポリフタルアミド樹脂のいずれかにより構成されている、
請求項1乃至7のいずれかに記載の半導体装置。 - 前記封止部材は、エポキシ系樹脂により構成されている、
請求項1乃至8のいずれかに記載の半導体装置。 - 前記封止部材は、無機フィラーを含んでいる、
請求項9に記載の半導体装置。 - 前記外部接続端子の厚さは、200μm以上、500μm以下であり、
段差を構成する、前記端子配置部の前記配置面から前記外部接続端子の前記おもて面までの段差高さは、50μm以上、125μm以下である、
請求項1に記載の半導体装置。
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