JP6079000B2 - 半導体パッケージ - Google Patents
半導体パッケージ Download PDFInfo
- Publication number
- JP6079000B2 JP6079000B2 JP2012142783A JP2012142783A JP6079000B2 JP 6079000 B2 JP6079000 B2 JP 6079000B2 JP 2012142783 A JP2012142783 A JP 2012142783A JP 2012142783 A JP2012142783 A JP 2012142783A JP 6079000 B2 JP6079000 B2 JP 6079000B2
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- Prior art keywords
- conductor
- semiconductor element
- heat
- multilayer substrate
- ceramic multilayer
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Description
図1は、この発明に係る実施の形態1による半導体パッケージの構成を示す図である。図1において、実施の形態1による半導体パッケージ20は、セラミック多層基板1と、板状のキャリア2と、枠状のリング9から構成される。キャリア2は、鉄ニッケルコバルト合金のように、セラミック多層基板1と線膨張率が近い金属からなる。セラミック多層基板1は、キャリア2の上面に、ろう材により接合される。リング9は、鉄ニッケルコバルト合金のように、セラミック多層基板1と線膨張率が近い金属からなる。リング9は、セラミック多層基板1の上面に対し、ろう材やはんだにより接合される。セラミック多層基板1におけるリング9の外側には、パッケージ外側端子(図示せず)が設けられる。
半導体素子3aは、例えばFETの回路が形成される。このFETが動作する際に、そのソース端子とドレイン端子の間で熱を発生する。発生した熱は、半導体素子3aの基材となるGaN、SiCまたはGaAsを伝わり、セラミック多層基板1との接合層5に熱を伝える。半導体素子3aが接合層5を介して接合される導体パターン6の表面には、Niめっき、Auめっきが施されているため、半導体素子3aの熱は当該めっき層を通して、導体パターン6から大口径VIA7に伝熱される。
図2は、この発明に係る実施の形態2による半導体パッケージの構成を示す図である。実施の形態2による半導体パッケージ30は、少なくとも2つの半導体素子3a、3bの間で、大口径VIA7を意図的にずらして配置することにより、放熱経路を一意に決定することができ、特定部位のパッケージの温度上昇を抑制し、温度変化に弱い方の半導体素子3bを、高発熱性の半導体素子3aによる発熱から保護することができる。
Claims (1)
- 高発熱性の第1の半導体素子と温度変化に弱い第2の半導体素子がそれぞれ接合層を介して異なる位置に載置される多層セラミック基板であって、
上記多層セラミック基板の上層に形成された複数の穴にそれぞれ充填され、上記第1の半導体素子の発熱部の直下に配置される接合層の直下に設けられた複数のビアをなす第1の導体柱と、
上記第1の導体柱の下に接続される上記多層セラミック基板内層の導体パターンと、
上記第1の導体柱の下で上記導体パターンに接続され、上記多層基板の下層に形成された穴に充填される上記第1の導体柱よりも径の小さい複数の第2の導体柱を備え、
上記第1の導体柱は上記第2の導体柱よりも径が2倍以上大きく、かつ上記第1の導体柱の径は隣接する他の第1の導体柱との間隙よりも大きく、上記複数の第2の導体柱の一部は上記第2の半導体素子の下に配置され、かつ上記第1の導体柱が上記第2の半導体素子の直下からずれて配置された多層セラミック基板
を備えた半導体パッケージ。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012142783A JP6079000B2 (ja) | 2012-06-26 | 2012-06-26 | 半導体パッケージ |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012142783A JP6079000B2 (ja) | 2012-06-26 | 2012-06-26 | 半導体パッケージ |
Publications (2)
Publication Number | Publication Date |
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JP2014007323A JP2014007323A (ja) | 2014-01-16 |
JP6079000B2 true JP6079000B2 (ja) | 2017-02-15 |
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JP2012142783A Active JP6079000B2 (ja) | 2012-06-26 | 2012-06-26 | 半導体パッケージ |
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Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
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KR102379703B1 (ko) * | 2014-08-14 | 2022-03-29 | 삼성전자주식회사 | 반도체 패키지 |
CN110972388A (zh) * | 2018-09-28 | 2020-04-07 | 广州灵派科技有限公司 | 一种高效散热的pcb板 |
JP7091555B2 (ja) | 2019-04-01 | 2022-06-27 | ヌヴォトンテクノロジージャパン株式会社 | 電力増幅装置 |
EP4044221A1 (en) * | 2021-02-10 | 2022-08-17 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Heat removal architecture for stack-type component carrier with embedded component |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3322432B2 (ja) * | 1992-03-11 | 2002-09-09 | 株式会社東芝 | 多層配線基板 |
JP3668083B2 (ja) * | 1999-12-27 | 2005-07-06 | 京セラ株式会社 | セラミック配線基板 |
JP2002184915A (ja) * | 2000-12-18 | 2002-06-28 | Hitachi Ltd | Lsiの放熱方式 |
JP2010080572A (ja) * | 2008-09-25 | 2010-04-08 | Denso Corp | 電子装置 |
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