JP5997234B2 - 半導体装置、電界効果トランジスタおよび電子装置 - Google Patents
半導体装置、電界効果トランジスタおよび電子装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 332
- 230000005669 field effect Effects 0.000 title claims description 14
- 239000000203 mixture Substances 0.000 claims description 90
- 230000010287 polarization Effects 0.000 claims description 38
- 239000000758 substrate Substances 0.000 claims description 38
- 150000004767 nitrides Chemical class 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims 1
- 229910052759 nickel Inorganic materials 0.000 claims 1
- 230000000149 penetrating effect Effects 0.000 claims 1
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- 230000015556 catabolic process Effects 0.000 description 10
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- 239000013078 crystal Substances 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 6
- 230000002269 spontaneous effect Effects 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000014509 gene expression Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000001629 suppression Effects 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910021478 group 5 element Inorganic materials 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- -1 nitride compound Chemical class 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 230000007480 spreading Effects 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
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- 238000001894 space-charge-limited current method Methods 0.000 description 1
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Description
xp2×Na=xn2×Nd2・・・(1B)
基板と、第1のn型半導体層と、p型半導体層と、第2のn型半導体層と、ドレイン電極と、ソース電極と、ゲート電極と、ゲート絶縁膜とを含み、
前記基板上に、前記第1のn型半導体層、前記p型半導体層、および前記第2のn型半導体層が、前記順序で積層され、
前記ドレイン電極は、前記第1のn型半導体層とオーミック接合され、
前記ソース電極は、前記第2のn型半導体層とオーミック接合され、
前記p型半導体層および前記第2のn型半導体層の一部に、前記第2のn型半導体層上面から前記第1のn型半導体層上部まで達する開口埋め込み部または切欠き部が形成され、
前記ゲート絶縁膜が、前記開口埋め込み部または切欠き部を覆うように形成され、
前記ゲート電極は、前記ゲート絶縁膜を介して前記開口埋め込み部または切欠き部を埋め込むように配置されることにより、前記ゲート絶縁膜を介して前記開口埋め込み部内面または前記切欠き部表面における前記第1のn型半導体層上面、前記p型半導体層側面および前記第2のn型半導体層側面と接合され、
前記p型半導体層は、前記ドレイン電極、前記ソース電極、および前記ゲート電極のいずれにも電圧を印加しない状態で、前記第1のn型半導体層側に正の分極電荷を有することを特徴とする。
図1の断面図に、本発明の半導体装置の一実施形態の構造を示す。本実施形態の半導体装置は、縦型GaN FETである。同図は、本実施形態における前記縦型GaN FETの半導体構造を模式的に示したものである。
図1に示す本実施形態の半導体装置である縦型GaN FETの製造方法について説明する。
以下、図1に示す本実施形態の半導体装置の作用、効果、変形例等について、例示的に説明する。
Nd1:前記第1のn型半導体層の不純物濃度(cm−3)
Nd2:前記第2のn型半導体層の不純物濃度(cm−3)
Na :前記p型半導体層の不純物濃度(cm−3)
Lch:前記p型半導体層の厚み(cm)
q:素電荷(電気素量)(C)
εs:前記半導体層の誘電率(F/cm)
Vbi:内蔵電位(V)
VB:前記半導体装置の耐圧(V)
図9の断面図に、本実施形態の半導体装置の構造を模式的に示す。この半導体装置は、図1の半導体装置と同じく縦型GaN FETである。図9に示すとおり、この半導体装置は、さらに、半導体から形成された組成変調層6を含む。組成変調層6は、n型GaN層2(前記第1のn型半導体層)上面とp型InGan層3(前記p型半導体層)下面とに接して第1のn型GaN層2とp型GaN層3との間に配置されている。この半導体装置は、n型GaN層2と組成変調層6との界面、前記組成変調層、およびp型InGaN層3と前記組成変調層との界面を形成する半導体の組成が、基板1平面と垂直な方向に、前記半導体の組成が連続的または段階的に変化する。組成変調層6下面付近は、n型GaN層2と組成がほぼ等しく、組成変調層6上面付近は、p型InGaN層3と組成がほぼ等しい。また、図9における組成変調層6は、n型半導体から形成されたn型組成変調層である。これら以外は、図9の半導体装置の構造は、図1の半導体装置と同様である。
本実施形態の半導体装置の製造方法は、例えば以下の通りである。まず、導電性Siから形成されたn型基板1上に、例えば、分子線エピタキシ(Molecular Beam Epitaxy: MBE)成長法により各半導体層を形成する。具体的には、n型基板1側から順に、n型GaNドリフト層2(膜厚1μm、ドーピング濃度1×1017cm−3)、n型組成変調層6(膜厚50nm、ドーピング濃度1×1017cm−3)、p型In0.2Ga0.8Nチャネル層3(膜厚0.1μm、ドーピング濃度5×1017cm−3)、およびn型GaNキャップ層4(膜厚0.1μm、ドーピング濃度5×1017cm−3)を、前記順序で積層させる。
以下、図9に示す本実施形態の半導体装置の作用、効果、変形例等について、例示的に説明する。
さらに、半導体から形成された組成変調層を含み、
前記第1のn型半導体層と前記p型半導体層とが異なる組成を有し、
前記組成変調層は、前記第1のn型半導体層上面と前記p型半導体層下面とに接して前記第1のn型半導体層と前記p型半導体層との間に配置され、
前記第1のn型半導体層と前記組成変調層との界面、前記組成変調層、および前記p型半導体層と前記組成変調層との界面を形成する半導体の組成が、前記基板平面と垂直な方向に連続的または段階的に変化し、
前記p型半導体層に代えて、前記p型半導体層と前記組成変調層との積層体が、前記ドレイン電極、前記ソース電極、および前記ゲート電極のいずれにも電圧を印加しない状態で、前記第1のn型半導体層側に正の分極電荷を有することが好ましい。これにより、例えば図10で説明したように、前記第1のn型半導体層と前記p型半導体層との間のノッチを解消または低減でき、さらに低抵抗を実現することが可能である。
2 n型GaN層(n型GaNドリフト層)
3 p型InGaN層(p型InGaNチャネル層)
4 n型GaN層(n型GaNキャップ層)
5 n型電導領域
6 n型組成変調層
7 高濃度n型GaN層
11 ソース電極
12 ゲート電極
13 ドレイン電極
21 ゲート絶縁膜
101 高濃度n型GaN基板
101' i型GaN層
102 n型GaN層
103 p型GaN層(p型GaNチャネル層)
104 n型GaN層(n型GaNキャップ層)
107 高濃度n型GaN層
110 サファイア基板
111 ソース電極
112 ゲート電極
113 ドレイン電極
121 ゲート絶縁膜
Claims (10)
- ドレイン領域として用いられる第1n型半導体層と、
前記第1n型半導体層上に積層され、チャネル領域として用いられるp型半導体層と、
前記p型半導体層上に積層され、ソース領域として用いられる第2n型半導体層と、
前記第2n型半導体層上面から前記p型半導体層を介して前記第1n型半導体層上部まで貫通する開口部と、
前記開口部内の表面に形成されたゲート絶縁膜と、
前記ゲート絶縁膜上に形成され、前記開口部を埋め込むように形成されたゲート電極と、
前記第1n型半導体層がAlxGa1−xN(但し、xは、0≦x≦1)で表される組成を有し、
前記p型半導体層がInyGa1−yN(但し、yは、0<y≦1)で表される組成を有し、
前記第2n型半導体層がAlzGa1−zN(但し、zは、0≦z≦1)で表される組成を有し、
前記ゲート電極が金属であり、
前記p型半導体層のIn組成比yが0.022より大きい半導体装置。 - ソース電極が前記第2n型半導体層上に形成され、
オーミック接合されていることを特徴とする請求項1に記載の半導体装置。 - 前記ソース電極と前記ゲート電極の間に、前記ゲート絶縁膜の一部が配置されていることを特徴とする請求項2に記載の半導体装置。
- 前記第1n型半導体層の下にn型基板が形成され、
前記n型基板の下にドレイン電極を形成され、
オーミック接合されていることを特徴とする請求項1〜3のいずれか一項に記載の半導体装置。 - 前記p型半導体層は、前記第2n型半導体層側に負の分極電荷を有する請求項1〜4のいずれか一項に記載の半導体装置。
- 前記第1n型半導体層と前記p型半導体層とが異なる組成を有する請求項1〜5のいずれか一項に記載の半導体装置。
- 前記第1n型半導体層、前記p型半導体層および前記第2n型半導体層が、III−V族窒化物半導体から形成されている請求項1〜6のいずれか一項に記載の半導体装置。
- 前記ゲート電極は、NiおよびAuの金属で形成されていることを特徴とする請求項1〜7のいずれか一項に記載の半導体装置。
- 電界効果トランジスタである請求項1〜8のいずれか一項に記載の半導体装置。
- 請求項1〜9のいずれか一項に記載の半導体装置を含む電子装置。
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