WO2011036921A1 - 半導体装置、電界効果トランジスタおよび電子装置 - Google Patents
半導体装置、電界効果トランジスタおよび電子装置 Download PDFInfo
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- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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- H01L29/1025—Channel region of field-effect devices
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- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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- H01L29/41725—Source or drain electrodes for field effect devices
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Definitions
- the present invention relates to a semiconductor device, a field effect transistor, and an electronic device.
- FETs field effect transistors
- FIG. 11A shows an example of the structure of a field effect transistor.
- FIG. 1 is a cross-sectional view schematically showing a semiconductor structure of a vertical GaN field effect transistor (hereinafter referred to as a vertical GaN FET) described in Non-Patent Document 1. As shown in the figure, this vertical GaN FET has an i-type GaN layer 101 'laminated on the upper surface of the sapphire substrate 110, and a high-concentration n-type GaN layer 107 laminated on the upper surface.
- a vertical GaN field effect transistor hereinafter referred to as a vertical GaN FET
- an n-type GaN layer 102, a p-type GaN layer 103, and an n-type GaN layer 104 are stacked in the above order.
- a drain electrode 113 is in ohmic contact with a part of the other part of the upper surface of the high-concentration n-type GaN layer 107.
- a source electrode 111 is ohmically joined to the upper surface of the n-type GaN layer 104.
- the side surface of the n-type GaN layer 102, the side surface of the p-type GaN layer 103, the upper surface and the side surface of the n-type GaN layer 104, 121 are stacked.
- An upper portion of the n-type GaN layer 102, the p-type GaN layer 103, and the n-type GaN layer 104 are partially removed to form an opening embedded portion.
- the gate electrode 112 is formed so as to embed the opening buried portion via the gate insulating film 121, and is joined to the n-type GaN layer 102, the p-type GaN layer 103, and the n-type GaN layer 104.
- the concentration of electrons accumulated at the interface between the p-type GaN layer 103 and the gate insulating film 121 can be adjusted by changing the voltage applied to the gate electrode 112. Thereby, the current flowing between the source electrode 111 and the drain electrode 113 can be controlled, and the vertical FET operation can be performed.
- Patent Document 1 In a field effect transistor using a nitride compound semiconductor, a chip area is small and a high breakdown voltage operation is possible” is described (see “Problem” in the same document abstract). Section).
- Patent Document 2 it is described that “a low-resistance buffer layer is realized in an electronic device (power electronics element) that operates by passing an electric current through an SiC substrate and each nitride semiconductor layer”. “Problem” in the bibliography.
- Patent Document 3 it is described as “To provide a nitride semiconductor having a low element resistance and a high operating voltage” (“Problem” in the abstract of the same document).
- Patent Document 4 it is described that “a semiconductor element having a mesa portion in which polarization generated by stacking of semiconductor layers is reduced and carriers can move smoothly and having low electric resistance is provided” (summary of the same document). In the “Issue” section).
- the inventors of the present invention have made extensive studies focusing on suppressing the punch-through phenomenon in a semiconductor device such as a field effect transistor.
- the punch-through phenomenon is a phenomenon in which a large amount of substrate current that cannot be controlled by a gate electrode flows in a semiconductor device having a gate electrode.
- this will be described using a theoretical formula.
- FIG. 11B is an example of the structure of the vertical GaN FET
- FIG. 12 is a schematic diagram of the band energy distribution of the vertical GaN FET shown in FIG. 11B.
- an n-type GaN layer 102, a p-type GaN layer 103, and an n-type GaN layer 104 are stacked in the above order on the upper surface of a high-concentration n-type GaN substrate 101. Yes.
- a drain electrode 113 is ohmically joined to the lower surface of the high-concentration n-type GaN substrate 101.
- a source electrode 111 is ohmically joined to the upper surface of the n-type GaN layer 104.
- a gate insulating film 121 is laminated in addition to the junction portion of the source electrode 111.
- the upper part of the n-type GaN layer 102, the p-type GaN layer 103, and the n-type GaN layer 104 are partially removed.
- a gate insulating film 121 is formed so as to cover the upper surface of the n-type GaN layer 102, the side surface of the p-type GaN layer 103, and the side surface of the n-type GaN layer 104.
- the gate electrode 112 is bonded to the n-type GaN layer 102, the p-type GaN layer 103, and the n-type GaN layer 104 through the gate insulating film 121.
- the concentration of electrons accumulated at the interface between the p-type GaN layer 103 and the gate insulating film 121 can be adjusted by changing the voltage applied to the gate electrode 112. Thereby, the current flowing between the source electrode 111 and the drain electrode 113 can be controlled, and the vertical FET operation can be performed.
- the line between AB shown in FIG. 12 corresponds to the line between AB shown in FIG. 11B, that is, the band energy distribution of the semiconductor layer between the source electrode and the drain electrode.
- FIG. 12 shows a band energy distribution from the n-type GaN layer 102 to the n-type GaN layer 104 among the semiconductor layers. Further, V ds (V) shown in FIG. 12 represents the drain voltage.
- the thickness of the p-type GaN layer 103 is expressed as L ch (cm), and the impurity concentration is expressed as N a (cm ⁇ 3 ).
- the thickness of the n-type GaN layer 102 is expressed as L dr (cm), and the impurity concentration is expressed as N d1 (cm ⁇ 3 ). Further, the spread (depletion layer width) of the depletion layer from the pn junction surface of these semiconductor layers is expressed as x p1 (cm) and x n1 (cm), respectively.
- the depletion layer widths from the pn junction surfaces of the p-type GaN layer 103 and the n-type GaN layer 104 are represented as x p2 (cm) and x n2 (cm), respectively, and the impurity concentration of the n-type GaN layer 104 is represented by N d2 This is expressed as (cm ⁇ 3 ).
- the relationship of the following mathematical formulas (1) and (1B) is established between the depletion layer width and the impurity concentration.
- the breakdown voltage V B (V) of the vertical GaN FET shown in FIG. 11B can be designed by the thickness of the n-type GaN layer 102. That is, when the breakdown electric field of GaN is E crit (V / cm), the following formula (2) is established under the condition that the n-type GaN layer 102 is completely depleted. In the following equation (2), the meaning of each symbol is as follows: V bi : built-in potential (V), k: Boltzmann constant, T: temperature (K), q: elementary charge (C), ⁇ s : dielectric constant of semiconductor layer (F / cm).
- the on-resistance R ON ( ⁇ ) of the vertical GaN FET shown in FIG. 11B can be approximately expressed by the following mathematical formula (3).
- q elementary charge (C)
- n carrier concentration (cm ⁇ 3 )
- ⁇ ch channel mobility (cm 2 / V ⁇ s)
- ⁇ n mobility in n-type GaN (Cm 2 / V ⁇ s).
- FIG. 13 shows the relationship between the calculated breakdown voltage V B (V) and the on-resistance R ON A (m ⁇ ⁇ cm 2 ).
- the horizontal axis indicates the breakdown voltage V B (V)
- the vertical axis indicates the on-resistance R ON A (m ⁇ ⁇ cm 2 ).
- x represents coordinates (cm) when the axis is taken in the direction perpendicular to the FET substrate plane (longitudinal direction).
- E (x) is an electric field at the coordinate x
- E n (x) represents an electric field when x is present in the n-type GaN layer 102
- E p (x) is an x-type.
- the electric field when present in the GaN layer 103 is represented.
- is expressed by the following mathematical formula (11).
- from the pn junction surface of the p-type GaN layer 103 and the n-type GaN layer 104 is expressed by the following formula (12).
- an object of the present invention is to provide a semiconductor device capable of suppressing the occurrence of a punch-through phenomenon.
- a semiconductor device of the present invention includes: A substrate, a first n-type semiconductor layer, a p-type semiconductor layer, a second n-type semiconductor layer, a drain electrode, a source electrode, a gate electrode, and a gate insulating film; On the substrate, the first n-type semiconductor layer, the p-type semiconductor layer, and the second n-type semiconductor layer are stacked in the order, The drain electrode is in ohmic contact with the first n-type semiconductor layer, The source electrode is in ohmic contact with the second n-type semiconductor layer, An opening embedded part or a notch part reaching from the upper surface of the second n-type semiconductor layer to the upper part of the first n-type semiconductor layer is formed in a part of the p-type semiconductor layer and the second n-type semiconductor layer.
- the gate insulating film is formed so as to cover the opening embedded portion or the cutout portion;
- the gate electrode is disposed so as to embed the opening embedded part or the notch part through the gate insulating film, so that the inner surface of the opening embedded part or the surface of the notch part through the gate insulating film is provided. Bonded to the upper surface of the first n-type semiconductor layer, the side surface of the p-type semiconductor layer, and the side surface of the second n-type semiconductor layer;
- the p-type semiconductor layer has a positive polarization charge on the first n-type semiconductor layer side in a state where no voltage is applied to any of the drain electrode, the source electrode, and the gate electrode. To do.
- the electronic device of the present invention includes the semiconductor device of the present invention.
- a semiconductor device capable of suppressing the occurrence of a punch-through phenomenon can be provided.
- FIG. 7 is a cross-sectional view showing a modification of the semiconductor device of FIG.
- FIG. 7 is a cross-sectional view showing another modification of the semiconductor device of FIG. 1.
- FIG. 10 is a cross-sectional view showing still another modification of the semiconductor device of FIG. 1.
- FIG. 10 is a cross-sectional view showing still another modification of the semiconductor device of FIG. 1.
- the semiconductor device of the present invention will be described in more detail based on specific embodiments.
- the following embodiments are merely examples, and the present invention is not limited to these descriptions.
- the above and following formulas are only theoretical formulas, and the phenomenon that occurs in the actual semiconductor device of the present invention may not completely match the formulas.
- the drawing showing the structure of the semiconductor device is an exemplary schematic diagram for convenience of description, and therefore, the size ratio of each part, the structure of details, and the like may be different from those of an actual semiconductor device.
- the numerical value may be strictly, or may be approximately the numerical value.
- FIG. 1 shows the structure of an embodiment of the semiconductor device of the present invention.
- the semiconductor device of this embodiment is a vertical GaN FET. This figure schematically shows the semiconductor structure of the vertical GaN FET in the present embodiment.
- the vertical GaN FET of this embodiment includes an n-type substrate 1 made of Si or the like, an n-type GaN layer (n-type GaN drift layer) 2, and a p-type InGaN layer (p-type InGaN channel layer). ) 3, n-type GaN layer 4 (n-type InGaN cap layer), drain electrode 13, source electrode 11, and gate electrode 12.
- the n-type GaN layer 2 corresponds to the “first n-type semiconductor layer” in the semiconductor device of the present invention.
- the p-type InGaN layer 3 corresponds to the “p-type semiconductor layer” in the semiconductor device of the present invention.
- the n-type GaN layer 4 corresponds to the “second n-type semiconductor layer” in the semiconductor device of the present invention.
- the vertical GaN FET of this embodiment further includes a gate insulating film 21.
- an n-type GaN layer 2 (first n-type semiconductor layer), a p-type InGaN layer 3 (p-type semiconductor layer), and an n-type GaN layer 4 (second n-type) are grown.
- Type semiconductor layers) are stacked in the above order.
- the upper surface of the n-type GaN layer 2 is in contact with the lower surface of the p-type InGaN layer 3.
- the upper surface of the p-type InGaN layer 3 is in contact with the lower surface of the n-type GaN layer 4.
- the drain electrode 13 is formed on the lower surface of the n-type substrate 1 and is in ohmic contact with the n-type GaN layer 2 (first n-type semiconductor layer).
- the source electrode 11 is formed on the upper surface of the n-type GaN layer 4 (second n-type semiconductor layer) and is in ohmic contact with the n-type GaN layer 4. A part of the upper part of the n-type GaN layer 2 and a part of the p-type InGaN layer 3 and the n-type GaN layer 4 are removed.
- the gate insulating film 21 is formed so as to cover the removed portion.
- the gate electrode 12 is disposed so as to embed the removed portion, and the upper surface of the n-type GaN layer 2 (first n-type semiconductor layer) and the p-type InGaN layer 3 (on the surface of the removed portion via the gate insulating film 21.
- the p-type InGaN layer 3 (p-type semiconductor layer) is an n-type GaN layer 2 (first n-type semiconductor layer) in a state where no voltage is applied to any of the drain electrode 13, the source electrode 11, and the gate electrode 12. It has a positive polarization charge on the side.
- an arrow between symbols AB represents a direction perpendicular to the plane of the substrate 1 from above the source electrode 11 to below the drain electrode 13.
- the other arrows are arrows that schematically illustrate the direction of current.
- the vertical GaN FET of this embodiment a plurality of the structures shown in FIG. That is, in the figure, the source electrode 11 is shown at the center of the vertical GaN FET and the gate electrode 12 is shown on the left and right, but the left and right gate insulating films 21 and the gate electrode 12 are connected to each other.
- One gate insulating film and a gate electrode are formed. That is, a part of the upper part of the n-type GaN layer 2 and a part of the p-type InGaN layer 3 and the n-type GaN layer 4 are removed to form an embedded opening, and the gate insulating film 21 It is formed to cover.
- the gate electrode 12 is disposed so as to embed the opening buried portion via the gate insulating film 21, whereby the n-type GaN layer 2 (first n-type layer) on the inner surface of the opening buried portion via the gate insulating film 21.
- the semiconductor layer is bonded to the upper surface, the p-type InGaN layer 3 (p-type semiconductor layer) side surface, and the n-type GaN layer 4 (second n-type semiconductor layer) side surface. That is, in the present embodiment, the gate electrodes 12 and the source electrodes 11 are alternately arranged in a plane on the top of the vertical GaN FET.
- “joining” may be in a direct contact state or in a state of being connected via other components.
- the state in which the electrode is bonded to the semiconductor layer is a state in which the source electrode 11 is in direct contact with the n-type GaN layer 4, and the drain electrode 13 is n through the n-type substrate 1.
- “upper side” is not limited to a state in which it is in direct contact with the upper surface (on) unless otherwise specified, and there is another component in between and direct contact. Also includes the state that is not (above). Similarly, “lower side” may be in a state of being in direct contact with the lower surface (on) unless otherwise specified, or in a state in which there are other components in between and there is no direct contact. (Below) is acceptable.
- “on the upper surface” refers to a state of being in direct contact with the upper surface.
- “on the lower surface” refers to a state of being in direct contact with the lower surface.
- At the one side may be in a state where it is in direct contact with one side unless otherwise specified, or may be in a state where there are other components in between and there is no direct contact. . The same applies to “at the both side”. “On the one side” refers to the state of direct contact with one side. The same applies to “on the both side”.
- composition refers to a quantitative relationship of the number of atoms of elements constituting a semiconductor layer or the like.
- Composition ratio refers to a relative ratio between the number of atoms of a specific element constituting the semiconductor layer and the like and the number of atoms of another element.
- Al composition ratio the numerical value of x is referred to as “Al composition ratio”.
- an impurity (dopant) for developing conductivity is not considered as an element constituting the semiconductor layer.
- a p-type GaN layer and an n-type GaN layer are different in impurities (dopants) but have the same composition.
- impurities dopants
- their compositions are assumed to be the same.
- each semiconductor constituting the first n-type semiconductor layer, the p-type semiconductor layer, the second n-type semiconductor layer and the like is not particularly limited, but is preferably in a crystalline state.
- the crystal state may be a single crystal state or a polycrystalline state, but is preferably a single crystal state.
- each of the semiconductor layers is formed on an n-type substrate 1 made of conductive Si by, for example, a molecular beam epitaxy (MBE) growth method.
- MBE molecular beam epitaxy
- the n-type GaN drift layer 2 film thickness: 1 ⁇ m, doping concentration: 1 ⁇ 10 17 cm ⁇ 3
- p-type In 0.2 Ga 0.8 N channel layer 3 in order from the n-type substrate 1 side
- an n-type GaN cap layer 4 film thickness of 0.1 ⁇ m and a doping concentration of 5 ⁇ 10 17 cm ⁇ 3 are stacked in this order.
- a metal such as Ti / Al is vapor-deposited on the upper surface of the n-type GaN layer 4 and the lower surface of the n-type substrate 1 to form the source electrode 11 and the drain electrode 13.
- annealing is performed at 650 ° C. to obtain ohmic contact (ohmic junction).
- a part of the epitaxial layer structure formed from the layers 2, 3, and 4 is removed by etching until the n-type GaN drift layer 2 is exposed.
- a metal such as Ni / Au is deposited to form the gate electrode 12.
- the vertical GaN FET shown in FIG. 1 can be manufactured.
- the above explanation is an example, and the vertical GaN FET of FIG. 1 may be manufactured by other manufacturing methods.
- the method for manufacturing a semiconductor device of the present invention is not particularly limited, and any manufacturing method can be applied with reference to, for example, a general method for manufacturing a semiconductor device.
- FIG. 2 is a schematic view illustrating the band energy distribution of the vertical GaN FET of this embodiment. 2 corresponds to the band energy distribution of the semiconductor layer between the line A and B shown in FIG. 1, that is, between the source electrode and the drain electrode.
- FIG. 2 shows a band energy distribution from the n-type GaN layer 2 to the n-type GaN layer 4 among the semiconductor layers.
- V ds shown in FIG. 2 shows a drain voltage (V) of the vertical GaN FET of FIG. 1
- V bi represents the built-in potential (V) of the vertical GaN FET of FIG.
- the p-type InGaN layer 3 is formed on the n-type GaN layer 2, so that no voltage is applied to any of the drain electrode 13, the source electrode 11, and the gate electrode 12.
- positive (+) polarization charges are generated at the lower interface of the p-type InGaN layer 3 and negative ( ⁇ ) polarization charges are generated at the upper interface.
- the expansion (spreading) of the depletion layer on the lower side (n-type GaN layer 2 side) in the p-type InGaN layer 3 can be suppressed, and punch-through resistance can be increased.
- the interface charge P sp (In y Ga 1-y N / GaN) (C ⁇ m ⁇ 2 ) originating from spontaneous polarization is expressed by the following formula (17) from formulas (14) and (15). Can be derived as follows.
- the polarization charge ⁇ (C ⁇ m ⁇ 2 ) generated at the lower interface of the p-type InGaN layer 3 can be derived from the equations (16) and (17) as the following equation (18).
- FIG. 3 is a graph illustrating charge density design by piezo polarization and spontaneous polarization in the semiconductor device of the present invention.
- the thickness of the p-type semiconductor layer is not particularly limited, but is preferably thinner from the viewpoint of reducing the on-resistance, and is a certain thickness or more from the viewpoint of suppressing the occurrence of the punch-through phenomenon. It is preferable.
- the p-type semiconductor layer is on the first n-type semiconductor layer side in a state where no voltage is applied to any of the drain electrode, the source electrode, and the gate electrode. Have a positive polarization charge. Thereby, since the occurrence of the punch-through phenomenon can be suppressed even when the p-type semiconductor layer is thin, it is possible to achieve both the reduction of the on-resistance and the suppression of the occurrence of the punch-through phenomenon.
- the band energy is increased by the polarization charge generated in the p-type InGaN layer 3, and the spread of the depletion layer due to the application of the drain voltage can be suppressed.
- the p-type InGaN layer 3 can be thinned while suppressing the occurrence of the punch-through phenomenon.
- the p-type InGaN layer 3 can be made thinner than the semiconductor device shown in FIG. 11A or 11B related to the present invention, and the on-resistance can be reduced. be able to.
- the vertical GaN FET of this embodiment uses the p-type InGaN layer 3 in which In is added to the p-type layer, it is possible to increase the concentration of the p-type dopant (impurities) and to generate a punch-through phenomenon.
- the p-type InGaN layer 3 can be thinned while suppressing the on-resistance.
- the thickness of the p-type semiconductor layer preferably satisfies the following mathematical formula (A) from the viewpoint of suppressing the occurrence of the punch-through phenomenon.
- the following mathematical formula (A) is the same as the mathematical formula (13).
- the meaning of each symbol is as follows.
- N d1 Impurity concentration (cm ⁇ 3 ) of the first n-type semiconductor layer
- N d2 impurity concentration of the second n-type semiconductor layer (cm ⁇ 3 )
- N a impurity concentration (cm ⁇ 3 ) of the p-type semiconductor layer
- L ch thickness of the p-type semiconductor layer (cm)
- q Elementary charge (elementary charge)
- C) ⁇ s dielectric constant of the semiconductor layer (F / cm)
- V bi Built-in potential (V)
- V B breakdown voltage (V) of the semiconductor device
- FIG. 4 shows the hole concentration distribution of the semiconductor device of this embodiment (FIG. 1) and another semiconductor device manufactured as a reference example.
- a semiconductor device having the structure of FIG. 11B was manufactured by the same manufacturing method as described above.
- the semiconductor structure of the semiconductor device of this reference example has an n-type GaN drift layer 102 (film thickness 1 ⁇ m, doping concentration 1 ⁇ 10 17 cm ⁇ 3 ), p-type GaN channel layer 103 in order from the n-type substrate 101 side in FIG. 11B. (Thickness 0.1 ⁇ m, doping concentration 5 ⁇ 10 17 cm ⁇ 3 ) and n-type GaN cap layer 104 (thickness 0.1 ⁇ m, doping concentration 5 ⁇ 10 17 cm ⁇ 3 ).
- the hole concentration in the p-type semiconductor layer (p-type GaN channel layer 103) is lower than the doping concentration (5 ⁇ 10 17 cm ⁇ 3 ).
- the active region is lost (that is, the entire p layer is depleted) and punch-through occurs.
- a region that is not depleted remains, and punch-through is suppressed.
- the first n-type semiconductor layer, the p-type semiconductor layer, and the second n-type semiconductor layer are not particularly limited, but are preferably formed of a III-V group nitride semiconductor.
- the group III-V nitride semiconductor may be a mixed crystal containing a group V element other than nitrogen, such as GaAsN, but a group III nitride semiconductor not containing a group V element other than nitrogen is preferable.
- Examples of the group III nitride semiconductor include GaN, InGaN, AlGaN, InAlN, and InAlGaN.
- the group III-V nitride semiconductor is more preferably a group III-V nitride semiconductor grown on Ga.
- the p-type semiconductor layer is positively polarized on the first n-type semiconductor layer side in a state where no voltage is applied to any of the drain electrode, the source electrode, and the gate electrode.
- the structure for having a charge is not particularly limited.
- the p-type layer and the first n-type semiconductor layer preferably have different compositions.
- the p-type semiconductor layer and the first n-type semiconductor layer have different interatomic distances between crystal lattices, which causes distortion in the crystal structure of the p-type semiconductor layer, and the positive polarization charge. Can be generated.
- the first n-type semiconductor layer has a composition represented by Al x Ga 1-x N (where x is 0 ⁇ x ⁇ 1), and the p-type semiconductor layer includes It is more preferable to have a composition represented by In y Ga 1-y N (where y is 0 ⁇ y ⁇ 1).
- the piezoelectric effect piezo polarization
- the Al composition ratio x is preferably 0 to 0.5, more preferably 0.05 to 0.4, and particularly preferably 0.1 to 0.3.
- the In composition ratio y of the p-type semiconductor layer represented by the composition of In y Ga 1-y N (where y is 0 ⁇ y ⁇ 1) is 0. It is preferably larger than 022.
- the p-type semiconductor layer is on the first n-type semiconductor layer side in a state where no voltage is applied to any of the drain electrode, the source electrode, and the gate electrode.
- the composition of the p-type semiconductor layer and the first n-type semiconductor layer may be the same.
- the p-type semiconductor layer preferably contains In.
- the p-type semiconductor layer is made of GaN and does not contain In, it is difficult for the p-type dopant (impurity) concentration to exceed 1 ⁇ 10 17 cm ⁇ 3 .
- the p-type semiconductor layer contains In, it is easy to dope the p-type dopant (impurities) in the p-type semiconductor layer at a high concentration as described above. If the p-type dopant (impurity) in the p-type semiconductor layer has a high concentration, as can be seen from the formula (A) (the formula (13)), even if the thickness of the p-type semiconductor layer is smaller, the punch It is easy to suppress the through phenomenon. This makes it easier to achieve both the suppression of the punch-through phenomenon and the reduction of the on-resistance.
- the impurity concentration N a (cm ⁇ 3 ) of the p-type semiconductor layer is, for example, 1 ⁇ 10 16 to 1 ⁇ 10 21 cm ⁇ 3 , preferably 1 ⁇ 10 17 to 1 ⁇ 10 20 cm ⁇ 3 , particularly preferably 1 ⁇ 10 18 to 1 ⁇ 10 19 cm ⁇ 3 .
- the preferable range of N a is the impurity concentration N d1 (cm ⁇ 3 ) of the first n-type semiconductor layer and the second n-type semiconductor layer. It is also influenced by other conditions such as the impurity concentration N d2 (cm ⁇ 3 ) of the semiconductor layer.
- N a are, for example, it may be set as appropriate by the formula (A) (Equation (13)) as a reference. Further, for example, as described with reference to FIG. 4 described above, the semiconductor device of the present embodiment has the same Na as that of the semiconductor device of the reference example, but due to the effect of the positive polarization charge according to the present invention, punch through The phenomenon is suppressed.
- the p-type semiconductor layer is negatively polarized on the second n-type semiconductor layer side in a state where no voltage is applied to any of the drain electrode, the source electrode, and the gate electrode. It preferably has a charge. Thereby, for example, as shown in FIG. 2, it is possible to suppress the expansion (spreading) of the depletion layer on the upper side (the second semiconductor layer side) of the p-type semiconductor layer. From this viewpoint, it is preferable that the composition of the p-type semiconductor layer and the composition of the second n-type semiconductor layer are different for the same reason as described for the positive polarization charge.
- the p-type semiconductor layer has a composition represented by In y Ga 1-y N (where y is 0 ⁇ y ⁇ 1), and the n-type semiconductor layer is Al z. It is more preferable to have a composition represented by Ga 1-z N (where z is 0 ⁇ z ⁇ 1).
- the Al composition ratio z is preferably 0 to 0.5, more preferably 0.05 to 0.4, and particularly preferably 0.1 to 0.3.
- the composition of the p-type semiconductor layer and the composition of the second n-type semiconductor layer may be the same.
- the p-type semiconductor layer of the semiconductor device of the present invention has a polarization charge on the first n-type semiconductor layer side
- the p-type semiconductor is not particularly limited to the first n-semiconductor layer side. This refers to the vicinity of the interface where the layer is in contact with the first semiconductor layer.
- the semiconductor device shown in FIG. 1 can be further modified in any way.
- the structure illustrated in FIG. 1 is illustrated as being continuous from side to side, but the structure alone illustrated in FIG. 1 may function as a semiconductor device (FET). That is, the semiconductor device (FET) of FIG. 1 has a notch instead of the opening buried portion, the gate insulating film is formed so as to cover the surface of the notch, and the gate electrode You may arrange
- the present invention is not limited to this, and in the semiconductor device of the present invention, the drain electrode, the source electrode, and the gate electrode may each be one or more. If there is at least one each of the drain electrode, the source electrode, and the gate electrode, it can function as a semiconductor device.
- the semiconductor device of the present invention preferably includes a plurality of at least one of the source electrode and the gate electrode, and the source electrode and the gate electrode are alternately arranged.
- the joining form of the ohmic electrodes is not limited to the form shown in FIG. 1, and various modifications are possible.
- an n-type conductive region is formed by ion implantation or the like in part or all of the upper part of the p-type semiconductor layer, and this is used as the second n-type semiconductor layer. Also good.
- An example is shown in FIG. In the semiconductor device (vertical GaN FET) of FIG. 5, n-type conductive regions 5 are formed on both the left and right sides of the upper portion of the p-type InGaN layer 3 by, for example, ion implantation.
- the n-type conductive region 5 is not formed in the upper central portion of the p-type InGaN layer 3.
- the semiconductor device of FIG. 5 does not have the second semiconductor layer 4.
- the source electrode 11 is in direct contact with the upper surfaces of the p-type InGaN layer 3 and the n-type conductive region 5 and is in ohmic contact with the p-type InGaN layer 3 and the n-type conductive region 5. Except for these points, the semiconductor device in FIG. 5 is the same as the semiconductor device in FIG.
- the source electrode may have a junction form as shown in FIG. 6, for example.
- a part of the n-type GaN layer 4 located below the source electrode 11 is removed to form a buried opening.
- the source electrode 11 is formed so as to embed the opening buried portion, and is in direct contact with both the n-type GaN layer 4 (the second semiconductor layer) and the p-type InGaN layer 3 (the p-type semiconductor layer), and n
- the ohmic junction is formed with the type GaN layer 4 and the p type InGaN layer 3.
- the semiconductor device of FIG. 6 is the same as the semiconductor device of FIG. 5 and 6 has a structure in which the second n-type semiconductor layer is stacked on part of the p-type semiconductor layer (upper surface).
- the drain electrode 13 is formed on the back surface of the n-type substrate 1 in FIG. 1, for example, as shown in FIG. 7, the drain electrode 13 can be formed so as to be connected to the n-type GaN layer 2 through a via hole or the like. It is.
- the structure of the semiconductor device in FIG. 7 will be described more specifically as follows. That is, first, in the semiconductor device shown in the figure, a part of the n-type substrate 1 is removed to form a via hole (opening buried portion). The drain electrode 13 is formed so as to contact the lower surface of the n-type substrate 1 and to directly contact the n-type GaN layer 2 (the first semiconductor layer) by filling the via hole (opening buried portion).
- the drain electrode 13 is in ohmic contact with the n-type GaN layer 2.
- the semiconductor device in FIG. 7 is the same as the semiconductor device in FIG.
- the via hole is not necessarily formed for each structure shown in FIG. If at least one via hole is formed for each semiconductor device, a corresponding effect can be obtained. However, a plurality of via holes may be formed, or may be formed for each structure shown in FIG.
- the drain electrode may have a bonding form other than bonding to the first n-type semiconductor layer through the substrate.
- a high concentration n-type GaN layer 7 for drain contact is provided below the n-type GaN layer 2 and a drain electrode 13 is formed on the upper surface of the high concentration n-type GaN layer 7 exposed from the surface side. It may be formed. That is, in the semiconductor device shown in the figure, the high concentration n-type GaN layer 7 is formed on the upper surface of the substrate 1.
- An n-type GaN layer 2 (the first n-type semiconductor layer) is formed on the upper surface of the high-concentration n-type GaN layer 7, a p-type InGaN layer 3 (the p-type semiconductor layer), and an n-type GaN layer 4.
- a structure similar to FIG. 1 is formed, such as (the second n-type semiconductor layer). This structure may be one or may be continuous from side to side. The structure is not formed on the upper surface of the high-concentration n-type GaN layer 7 at the left and right ends of the semiconductor device in FIG. Instead of the lower surface of the substrate 1, the drain electrode 13 is formed on the upper surface of the high-concentration n-type GaN layer 7, one at each of the left and right ends of the semiconductor device.
- the semiconductor device of the present invention may be used by arbitrarily combining the source electrode junction configuration shown in FIGS. 1, 5, and 6 and the drain electrode junction configuration shown in FIGS. 7 and 8. Good or other structures are acceptable.
- the structure of the semiconductor device of the present invention may be a structure based on the structure of the semiconductor device shown in FIG. 11A, for example.
- the formation material of the substrate, each semiconductor layer, and the like is not limited to the above formation material.
- the substrate is not limited to an n-type Si substrate, and may be a high-concentration n-type GaN substrate or the like, or is not limited to an n-type substrate, and may be a p-type substrate.
- the substrate does not have to be conductive, and a high-resistance or insulating substrate may be used. .
- the p-type InGaN layer 3 is positively polarized on the n-type GaN layer 2 side and negatively polarized on the n-type GaN layer 4 side. Each charge was generated. However, if the p-type InGaN layer 3 can generate a positive polarization charge on the n-type GaN layer 2 side, the composition of the n-type GaN layer 2, the p-type InGaN layer 3, and the n-type GaN layer 4 is It does not specifically limit and arbitrary compositions are applicable.
- the n-type GaN layer 2 has a composition represented by Al x Ga 1-x N (where x is 0 ⁇ x ⁇ 1), and the p-type InGaN layer 3 is In y Ga. 1-y N (where y is 0 ⁇ y ⁇ 1), and the n-type GaN layer 4 is Al z Ga 1-z N (where z is 0 ⁇ z ⁇ 1)
- Each of the layers may be formed so as to have a composition represented by:
- the semiconductor device of the present invention is not particularly limited, but is preferably a field effect transistor (FET). All the semiconductor devices described with reference to the above drawings can be used as field effect transistors (FETs).
- FIG. 9 schematically shows the structure of the semiconductor device of this embodiment.
- This semiconductor device is a vertical GaN FET like the semiconductor device of FIG.
- this semiconductor device further includes a composition modulation layer 6 formed of a semiconductor.
- the composition modulation layer 6 is in contact with the upper surface of the n-type GaN layer 2 (the first n-type semiconductor layer) and the lower surface of the p-type InGan layer 3 (the p-type semiconductor layer), and the first n-type GaN layer 2 and the p It is arranged between the type GaN layer 3.
- the composition of the semiconductor forming the interface between the n-type GaN layer 2 and the composition modulation layer 6, the composition modulation layer, and the interface between the p-type InGaN layer 3 and the composition modulation layer is The composition of the semiconductor changes continuously or stepwise in the vertical direction. In the vicinity of the lower surface of the composition modulation layer 6, the composition is substantially equal to that of the n-type GaN layer 2, and in the vicinity of the upper surface of the composition modulation layer 6, the composition is approximately equal to that of the p-type InGaN layer 3. Further, the composition modulation layer 6 in FIG. 9 is an n-type composition modulation layer formed of an n-type semiconductor. Except for these, the structure of the semiconductor device of FIG. 9 is similar to that of the semiconductor device of FIG.
- each semiconductor layer is formed on the n-type substrate 1 made of conductive Si by, for example, a molecular beam epitaxy (MBE) growth method.
- MBE molecular beam epitaxy
- an n-type GaN drift layer 2 (film thickness 1 ⁇ m, doping concentration 1 ⁇ 10 17 cm ⁇ 3 ), n-type composition modulation layer 6 (film thickness 50 nm, doping concentration 1 ⁇ 10 17 cm ⁇ 3 ), p-type In 0.2 Ga 0.8 N channel layer 3 (film thickness 0.1 ⁇ m, doping concentration 5 ⁇ 10 17 cm ⁇ 3 ), and n-type GaN cap layer 4 (film thickness 0). 1 ⁇ m and a doping concentration of 5 ⁇ 10 17 cm ⁇ 3 ) are stacked in the above order.
- a metal such as Ti / Al is deposited on the upper surface of the n-type GaN layer 4 and the lower surface of the n-type substrate 1 to form the source electrode 11 and the drain electrode 13, respectively.
- the source electrode 11 and the drain electrode 13 are brought into ohmic contact (ohmic junction) by annealing at 650 ° C. after formation.
- a part of the epitaxial layer structure formed from the layers 2, 3, 4 and 6 is removed by etching until the n-type GaN drift layer 2 is exposed.
- a metal such as Ni / Au is deposited to form the gate electrode 12.
- the vertical GaN FET shown in FIG. 9 can be manufactured.
- the vertical GaN FET of FIG. 9 may be manufactured by other manufacturing methods.
- the method for manufacturing a semiconductor device of the present invention is not particularly limited.
- the punch-through phenomenon can be suppressed by the polarization charge generated in the p-type InGaN layer 3 as in the first embodiment. Furthermore, in this embodiment, the n-type composition modulation layer 6 does not cause a notch (a phenomenon in which the band energy suddenly changes at the layer interface) between the n-type GaN layer 2 and the p-type InGaN layer 3. It becomes possible to do.
- FIG. 10 is a schematic view illustrating the band energy distribution of the vertical GaN FET of this embodiment.
- the line between AB shown in FIG. 10 corresponds to the line energy between AB shown in FIG. 9, that is, the band energy distribution of the semiconductor layer between the source electrode and the drain electrode.
- FIG. 10 shows a band energy distribution from the n-type GaN layer 2 to the n-type GaN layer 4 among the semiconductor layers.
- the stacked body of the p-type InGaN layer 3 and the composition modulation layer 6 is an n-type GaN layer in a state where no voltage is applied to any of the drain electrode, the source electrode, and the gate electrode. Has positive polarization charge on the 2 side.
- the total sum of positive polarization charges generated in the n-type composition modulation layer 6 and the p-type InGaN layer 3 is generated in the p-type InGaN layer 3 of the semiconductor device having the structure of the first embodiment based on the respective theoretical formulas. Equal to the positive polarization charge. Therefore, also in the present embodiment, as in the first embodiment, an effect of suppressing the punch-through phenomenon due to the positive polarization charge can be obtained. Furthermore, since the vertical GaN FET of this embodiment has no notch between the p-type InGaN layer 3 and the n-type GaN layer 2 due to the insertion of the n-type composition modulation layer 6, as shown in FIG. A resistance lower than 1 can be realized.
- the semiconductor device of the present invention is, for example, as shown in FIG. Furthermore, a composition modulation layer formed from a semiconductor is included, The first n-type semiconductor layer and the p-type semiconductor layer have different compositions; The composition modulation layer is disposed between the first n-type semiconductor layer and the p-type semiconductor layer in contact with the upper surface of the first n-type semiconductor layer and the lower surface of the p-type semiconductor layer, The composition of the semiconductor forming the interface between the first n-type semiconductor layer and the composition modulation layer, the composition modulation layer, and the interface between the p-type semiconductor layer and the composition modulation layer is perpendicular to the substrate plane.
- the stacked body of the p-type semiconductor layer and the composition modulation layer does not apply a voltage to any of the drain electrode, the source electrode, and the gate electrode. It is preferable that the n-type semiconductor layer 1 has a positive polarization charge. As a result, for example, as described with reference to FIG. 10, the notch between the first n-type semiconductor layer and the p-type semiconductor layer can be eliminated or reduced, and a low resistance can be realized.
- the composition modulation layer is not limited to n-type, and may be a p-type modulation layer, or an n-type composition modulation layer and a p-type composition modulation layer. It may be formed from both.
- the composition modulation layer is a p-type composition modulation layer and when it is formed of both an n-type composition modulation layer and a p-type composition modulation layer, the effect of eliminating or reducing the notch can be obtained in the same manner.
- the n-type composition modulation layer is disposed on the first n-type semiconductor layer side, and the p-type It is preferable that the composition modulation layer is disposed on the p-type semiconductor layer side. That is, it is preferable that the n-type composition modulation layer is in contact with the upper surface of the first n-type semiconductor layer, and the p-type composition modulation layer is in contact with the upper surface of the p-type semiconductor layer.
- the composition modulation layer is formed of one or both of an n-type composition modulation layer and a p-type composition modulation layer, and the lower surface of the n-type composition modulation layer is the first n-type semiconductor layer. It is preferable that the upper surface of the p-type composition modulation layer is in contact with the upper surface and the lower surface of the p-type semiconductor layer is in contact with the upper surface.
- the first n-semiconductor layer side is not particularly limited,
- the vicinity of the stacked body of the p-type semiconductor layer and the composition modulation layer is in contact with the upper surface of the first semiconductor layer.
- the vicinity includes only the composition modulation layer and may not include the p-type semiconductor layer, or may include the p-type semiconductor layer.
- another composition modulation layer similar to the composition modulation layer is disposed between the upper surface of the p-type semiconductor layer and the lower surface of the second n-type semiconductor layer. Also good.
- the other composition modulation layer is formed of one or both of an n-type composition modulation layer and a p-type composition modulation layer, and an upper surface of the n-type composition modulation layer is in contact with a lower surface of the second n-type semiconductor layer, The lower surface of the p-type composition modulation layer is preferably in contact with the upper surface of the p-type semiconductor layer.
- the other composition modulation layer may be used alone or in combination with the composition modulation layer disposed between the upper surface of the first n-type semiconductor layer and the lower surface of the p-type semiconductor layer.
- the semiconductor device (vertical GaN FET) of the present embodiment shown in FIG. 9 can be modified in various ways, for example, according to the various modifications described in the first embodiment.
- n-type conductivity is formed in a part of the p-type InGaN layer 3 by ion implantation or the like, and the source electrode 11 is formed so as to be in contact with both the n-type region and the p-type region. May be.
- a via hole or the like may be formed in a part of the n-type substrate 1, and the drain electrode 13 may be formed so as to be connected to the n-type InGaN layer 5.
- a semiconductor device capable of suppressing the occurrence of a punch-through phenomenon can be provided.
- the semiconductor device of the present invention can obtain a low on-resistance even in a low withstand voltage region, for example, by suppressing the punch-through phenomenon.
- the semiconductor device of the present invention is not particularly limited, but is preferably a field effect transistor (FET), and particularly preferably a vertical GaN FET.
- FET field effect transistor
- the use of the semiconductor device of the present invention is not particularly limited, and for example, it may be used for the same use as a general field effect transistor (FET).
- the semiconductor device of the present invention can be widely used in electronic devices such as various home appliances and communication equipment.
- n-type substrate 2 n-type GaN layer (n-type GaN drift layer) 3 p-type InGaN layer (p-type InGaN channel layer) 4 n-type GaN layer (n-type GaN cap layer) 5 n-type conductive region 6 n-type composition modulation layer 7 high-concentration n-type GaN layer 11 source electrode 12 gate electrode 13 drain electrode 21 gate insulating film 101 high-concentration n-type GaN substrate 101 ′ i-type GaN layer 102 n-type GaN layer 103 p-type GaN layer (p-type GaN channel layer) 104 n-type GaN layer (n-type GaN cap layer) 107 High-concentration n-type GaN layer 110 Sapphire substrate 111 Source electrode 112 Gate electrode 113 Drain electrode 121 Gate insulating film
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Abstract
Description
xp2×Na=xn2×Nd2・・・(1B)
基板と、第1のn型半導体層と、p型半導体層と、第2のn型半導体層と、ドレイン電極と、ソース電極と、ゲート電極と、ゲート絶縁膜とを含み、
前記基板上に、前記第1のn型半導体層、前記p型半導体層、および前記第2のn型半導体層が、前記順序で積層され、
前記ドレイン電極は、前記第1のn型半導体層とオーミック接合され、
前記ソース電極は、前記第2のn型半導体層とオーミック接合され、
前記p型半導体層および前記第2のn型半導体層の一部に、前記第2のn型半導体層上面から前記第1のn型半導体層上部まで達する開口埋め込み部または切欠き部が形成され、
前記ゲート絶縁膜が、前記開口埋め込み部または切欠き部を覆うように形成され、
前記ゲート電極は、前記ゲート絶縁膜を介して前記開口埋め込み部または切欠き部を埋め込むように配置されることにより、前記ゲート絶縁膜を介して前記開口埋め込み部内面または前記切欠き部表面における前記第1のn型半導体層上面、前記p型半導体層側面および前記第2のn型半導体層側面と接合され、
前記p型半導体層は、前記ドレイン電極、前記ソース電極、および前記ゲート電極のいずれにも電圧を印加しない状態で、前記第1のn型半導体層側に正の分極電荷を有することを特徴とする。
図1の断面図に、本発明の半導体装置の一実施形態の構造を示す。本実施形態の半導体装置は、縦型GaN FETである。同図は、本実施形態における前記縦型GaN FETの半導体構造を模式的に示したものである。
図1に示す本実施形態の半導体装置である縦型GaN FETの製造方法について説明する。
以下、図1に示す本実施形態の半導体装置の作用、効果、変形例等について、例示的に説明する。
Nd1:前記第1のn型半導体層の不純物濃度(cm-3)
Nd2:前記第2のn型半導体層の不純物濃度(cm-3)
Na :前記p型半導体層の不純物濃度(cm-3)
Lch:前記p型半導体層の厚み(cm)
q:素電荷(電気素量)(C)
εs:前記半導体層の誘電率(F/cm)
Vbi:内蔵電位(V)
VB:前記半導体装置の耐圧(V)
図9の断面図に、本実施形態の半導体装置の構造を模式的に示す。この半導体装置は、図1の半導体装置と同じく縦型GaN FETである。図9に示すとおり、この半導体装置は、さらに、半導体から形成された組成変調層6を含む。組成変調層6は、n型GaN層2(前記第1のn型半導体層)上面とp型InGan層3(前記p型半導体層)下面とに接して第1のn型GaN層2とp型GaN層3との間に配置されている。この半導体装置は、n型GaN層2と組成変調層6との界面、前記組成変調層、およびp型InGaN層3と前記組成変調層との界面を形成する半導体の組成が、基板1平面と垂直な方向に、前記半導体の組成が連続的または段階的に変化する。組成変調層6下面付近は、n型GaN層2と組成がほぼ等しく、組成変調層6上面付近は、p型InGaN層3と組成がほぼ等しい。また、図9における組成変調層6は、n型半導体から形成されたn型組成変調層である。これら以外は、図9の半導体装置の構造は、図1の半導体装置と同様である。
本実施形態の半導体装置の製造方法は、例えば以下の通りである。まず、導電性Siから形成されたn型基板1上に、例えば、分子線エピタキシ(Molecular Beam Epitaxy: MBE)成長法により各半導体層を形成する。具体的には、n型基板1側から順に、n型GaNドリフト層2(膜厚1μm、ドーピング濃度1×1017cm-3)、n型組成変調層6(膜厚50nm、ドーピング濃度1×1017cm-3)、p型In0.2Ga0.8Nチャネル層3(膜厚0.1μm、ドーピング濃度5×1017cm-3)、およびn型GaNキャップ層4(膜厚0.1μm、ドーピング濃度5×1017cm-3)を、前記順序で積層させる。
以下、図9に示す本実施形態の半導体装置の作用、効果、変形例等について、例示的に説明する。
さらに、半導体から形成された組成変調層を含み、
前記第1のn型半導体層と前記p型半導体層とが異なる組成を有し、
前記組成変調層は、前記第1のn型半導体層上面と前記p型半導体層下面とに接して前記第1のn型半導体層と前記p型半導体層との間に配置され、
前記第1のn型半導体層と前記組成変調層との界面、前記組成変調層、および前記p型半導体層と前記組成変調層との界面を形成する半導体の組成が、前記基板平面と垂直な方向に連続的または段階的に変化し、
前記p型半導体層に代えて、前記p型半導体層と前記組成変調層との積層体が、前記ドレイン電極、前記ソース電極、および前記ゲート電極のいずれにも電圧を印加しない状態で、前記第1のn型半導体層側に正の分極電荷を有することが好ましい。これにより、例えば図10で説明したように、前記第1のn型半導体層と前記p型半導体層との間のノッチを解消または低減でき、さらに低抵抗を実現することが可能である。
2 n型GaN層(n型GaNドリフト層)
3 p型InGaN層(p型InGaNチャネル層)
4 n型GaN層(n型GaNキャップ層)
5 n型電導領域
6 n型組成変調層
7 高濃度n型GaN層
11 ソース電極
12 ゲート電極
13 ドレイン電極
21 ゲート絶縁膜
101 高濃度n型GaN基板
101’ i型GaN層
102 n型GaN層
103 p型GaN層(p型GaNチャネル層)
104 n型GaN層(n型GaNキャップ層)
107 高濃度n型GaN層
110 サファイア基板
111 ソース電極
112 ゲート電極
113 ドレイン電極
121 ゲート絶縁膜
Claims (12)
- 基板と、第1のn型半導体層と、p型半導体層と、第2のn型半導体層と、ドレイン電極と、ソース電極と、ゲート電極と、ゲート絶縁膜とを含み、
前記基板上に、前記第1のn型半導体層、前記p型半導体層、および前記第2のn型半導体層が、前記順序で積層され、
前記ドレイン電極は、前記第1のn型半導体層とオーミック接合され、
前記ソース電極は、前記第2のn型半導体層とオーミック接合され、
前記p型半導体層および前記第2のn型半導体層の一部に、前記第2のn型半導体層上面から前記第1のn型半導体層上部まで達する開口埋め込み部または切欠き部が形成され、
前記ゲート絶縁膜が、前記開口埋め込み部または切欠き部を覆うように形成され、
前記ゲート電極は、前記ゲート絶縁膜を介して前記開口埋め込み部または切欠き部を埋め込むように配置されることにより、前記ゲート絶縁膜を介して前記開口埋め込み部内面または前記切欠き部表面における前記第1のn型半導体層上面、前記p型半導体層側面および前記第2のn型半導体層側面と接合され、
前記p型半導体層は、前記ドレイン電極、前記ソース電極、および前記ゲート電極のいずれにも電圧を印加しない状態で、前記第1のn型半導体層側に正の分極電荷を有することを特徴とする半導体装置。 - 前記p型半導体層が、前記ドレイン電極、前記ソース電極、および前記ゲート電極のいずれにも電圧を印加しない状態で、前記第2のn型半導体層側に負の分極電荷を有することを特徴とする請求の範囲1記載の半導体装置。
- 前記第1のn型半導体層と前記p型半導体層とが異なる組成を有することを特徴とする請求の範囲1または2記載の半導体装置。
- 前記第1のn型半導体層、前記p型半導体層および前記第2のn型半導体層が、III-V族窒化物半導体から形成されていることを特徴とする請求の範囲1から3のいずれか一項に記載の半導体装置。
- 前記第1のn型半導体層がAlxGa1-xN(但し、xは、0≦x≦1)で表される組成を有し、前記p型半導体層がInyGa1-yN(但し、yは、0<y≦1)で表される組成を有することを特徴とする請求の範囲1から4のいずれか一項に記載の半導体装置。
- 前記p型半導体層のIn組成比yが0.022より大きいことを特徴とする請求の範囲5記載の半導体装置。
- さらに、半導体から形成された組成変調層を含み、
前記第1のn型半導体層と前記p型半導体層とが異なる組成を有し、
前記組成変調層は、前記第1のn型半導体層上面と前記p型半導体層下面とに接して前記第1のn型半導体層と前記p型半導体層との間に配置され、
前記第1のn型半導体層と前記組成変調層との界面、前記組成変調層、および前記p型半導体層と前記組成変調層との界面を形成する半導体の組成が、前記基板平面と垂直な方向に連続的または段階的に変化し、
前記p型半導体層に代えて、前記p型半導体層と前記組成変調層との積層体が、前記ドレイン電極、前記ソース電極、および前記ゲート電極のいずれにも電圧を印加しない状態で、前記第1のn型半導体層側に正の分極電荷を有することを特徴とする請求の範囲1から7のいずれか一項に記載の半導体装置。 - 前記組成変調層は、n型組成変調層およびp型組成変調層の一方または両方から形成され、前記n型組成変調層の下面は前記第1のn型半導体層上面と接しており、前記p型組成変調層の上面は前記p型半導体層下面と接していることを特徴とする請求の範囲8記載の半導体装置。
- 前記開口埋め込み部または切欠き部は、前記p型半導体層および前記第2のn型半導体層の一部が除去されることにより形成されたものであることを特徴とする請求の範囲1から9のいずれか一項に記載の半導体装置。
- 電界効果トランジスタであることを特徴とする請求の範囲10記載の半導体装置。
- 請求の範囲1から11のいずれか一項に記載の半導体装置を含むことを特徴とする電子装置。
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