JP5976013B2 - Ｓｏｉ構造体のデバイス層中の金属含有量の減少方法、およびこのような方法により製造されるｓｏｉ構造体 - Google Patents

Ｓｏｉ構造体のデバイス層中の金属含有量の減少方法、およびこのような方法により製造されるｓｏｉ構造体 Download PDF

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JP5976013B2
JP5976013B2 JP2013551383A JP2013551383A JP5976013B2 JP 5976013 B2 JP5976013 B2 JP 5976013B2 JP 2013551383 A JP2013551383 A JP 2013551383A JP 2013551383 A JP2013551383 A JP 2013551383A JP 5976013 B2 JP5976013 B2 JP 5976013B2
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silicon
device layer
layer
sacrificial oxide
oxide layer
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JP2014508405A (ja
JP2014508405A5 (https=
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アレクシス・グラッベ
ローレンス・ピー・フラナリー
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SunEdison Inc
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SunEdison Inc
MEMC Electronic Materials Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H10P36/03—Gettering within semiconductor bodies within silicon bodies
    • H10P36/07—Gettering within semiconductor bodies within silicon bodies of silicon-on-insulator structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/10—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H10P36/03—Gettering within semiconductor bodies within silicon bodies

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  • Element Separation (AREA)
  • Weting (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Formation Of Insulating Films (AREA)
JP2013551383A 2011-01-31 2012-01-27 Ｓｏｉ構造体のデバイス層中の金属含有量の減少方法、およびこのような方法により製造されるｓｏｉ構造体 Active JP5976013B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201161437993P 2011-01-31 2011-01-31
US61/437,993 2011-01-31
US13/354,788 2012-01-20
US13/354,788 US8796116B2 (en) 2011-01-31 2012-01-20 Methods for reducing the metal content in the device layer of SOI structures and SOI structures produced by such methods
PCT/US2012/022970 WO2012106210A2 (en) 2011-01-31 2012-01-27 Methods for reducing the metal content in the device layer of soi structures and soi structures produced by such methods

Publications (3)

Publication Number Publication Date
JP2014508405A JP2014508405A (ja) 2014-04-03
JP2014508405A5 JP2014508405A5 (https=) 2015-02-26
JP5976013B2 true JP5976013B2 (ja) 2016-08-23

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JP2013551383A Active JP5976013B2 (ja) 2011-01-31 2012-01-27 Ｓｏｉ構造体のデバイス層中の金属含有量の減少方法、およびこのような方法により製造されるｓｏｉ構造体

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US (3) US8796116B2 (https=)
EP (1) EP2671247B1 (https=)
JP (1) JP5976013B2 (https=)
KR (1) KR101871534B1 (https=)
CN (1) CN103339713B (https=)
MY (1) MY166803A (https=)
SG (1) SG191966A1 (https=)
TW (1) TW201250838A (https=)
WO (1) WO2012106210A2 (https=)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9064789B2 (en) * 2013-08-12 2015-06-23 International Business Machines Corporation Bonded epitaxial oxide structures for compound semiconductor on silicon substrates
WO2015112308A1 (en) 2014-01-23 2015-07-30 Sunedison Semiconductor Limited High resistivity soi wafers and a method of manufacturing thereof
US9853133B2 (en) * 2014-09-04 2017-12-26 Sunedison Semiconductor Limited (Uen201334164H) Method of manufacturing high resistivity silicon-on-insulator substrate
US9899499B2 (en) 2014-09-04 2018-02-20 Sunedison Semiconductor Limited (Uen201334164H) High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss
EP3221885B1 (en) 2014-11-18 2019-10-23 GlobalWafers Co., Ltd. High resistivity semiconductor-on-insulator wafer and a method of manufacturing
WO2016081367A1 (en) 2014-11-18 2016-05-26 Sunedison Semiconductor Limited HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE COMPRISING A CHARGE TRAPPING LAYER FORMED BY He-N2 CO-IMPLANTATION
EP3221884B1 (en) 2014-11-18 2022-06-01 GlobalWafers Co., Ltd. High resistivity semiconductor-on-insulator wafers with charge trapping layers and method of manufacturing thereof
US10283402B2 (en) 2015-03-03 2019-05-07 Globalwafers Co., Ltd. Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress
WO2016149113A1 (en) 2015-03-17 2016-09-22 Sunedison Semiconductor Limited Thermally stable charge trapping layer for use in manufacture of semiconductor-on-insulator structures
US9881832B2 (en) 2015-03-17 2018-01-30 Sunedison Semiconductor Limited (Uen201334164H) Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof
EP3739620B1 (en) 2015-06-01 2022-02-16 GlobalWafers Co., Ltd. A silicon germanium-on-insulator structure
WO2016196060A1 (en) 2015-06-01 2016-12-08 Sunedison Semiconductor Limited A method of manufacturing semiconductor-on-insulator
JP6749394B2 (ja) * 2015-11-20 2020-09-02 グローバルウェーハズ カンパニー リミテッドＧｌｏｂａｌＷａｆｅｒｓ Ｃｏ．，Ｌｔｄ． 滑らかな半導体表面の製造方法
US9806025B2 (en) * 2015-12-29 2017-10-31 Globalfoundries Inc. SOI wafers with buried dielectric layers to prevent Cu diffusion
US10622247B2 (en) 2016-02-19 2020-04-14 Globalwafers Co., Ltd. Semiconductor on insulator structure comprising a buried high resistivity layer
US9831115B2 (en) 2016-02-19 2017-11-28 Sunedison Semiconductor Limited (Uen201334164H) Process flow for manufacturing semiconductor on insulator structures in parallel
WO2017142704A1 (en) 2016-02-19 2017-08-24 Sunedison Semiconductor Limited High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed on a substrate with a rough surface
US11848227B2 (en) 2016-03-07 2023-12-19 Globalwafers Co., Ltd. Method of manufacturing a semiconductor on insulator structure by a pressurized bond treatment
WO2017155806A1 (en) 2016-03-07 2017-09-14 Sunedison Semiconductor Limited Semiconductor on insulator structure comprising a plasma oxide layer and method of manufacture thereof
US11114332B2 (en) 2016-03-07 2021-09-07 Globalwafers Co., Ltd. Semiconductor on insulator structure comprising a plasma nitride layer and method of manufacture thereof
EP3427293B1 (en) 2016-03-07 2021-05-05 Globalwafers Co., Ltd. Semiconductor on insulator structure comprising a low temperature flowable oxide layer and method of manufacture thereof
EP3469120B1 (en) 2016-06-08 2022-02-02 GlobalWafers Co., Ltd. High resistivity single crystal silicon ingot and wafer having improved mechanical strength
US10269617B2 (en) 2016-06-22 2019-04-23 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising an isolation region
FR3057705B1 (fr) * 2016-10-13 2019-04-12 Soitec Procede de dissolution d'un oxyde enterre dans une plaquette de silicium sur isolant
WO2018080772A1 (en) 2016-10-26 2018-05-03 Sunedison Semiconductor Limited High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency
US10468295B2 (en) 2016-12-05 2019-11-05 GlobalWafers Co. Ltd. High resistivity silicon-on-insulator structure and method of manufacture thereof
KR102320673B1 (ko) * 2016-12-28 2021-11-01 인벤사스 본딩 테크놀로지스 인코포레이티드 적층된 기판의 처리
JP7110204B2 (ja) 2016-12-28 2022-08-01 サンエディソン・セミコンダクター・リミテッド イントリンシックゲッタリングおよびゲート酸化物完全性歩留まりを有するシリコンウエハを処理する方法
SG11201913769RA (en) 2017-07-14 2020-01-30 Sunedison Semiconductor Ltd Method of manufacture of a semiconductor on insulator structure
CN107946231B (zh) * 2017-11-22 2020-06-16 上海华力微电子有限公司 一种FDSOI器件SOI和bulk区域浅槽形貌优化方法
US10964664B2 (en) 2018-04-20 2021-03-30 Invensas Bonding Technologies, Inc. DBI to Si bonding for simplified handle wafer
SG11202009989YA (en) 2018-04-27 2020-11-27 Globalwafers Co Ltd Light assisted platelet formation facilitating layer transfer from a semiconductor donor substrate
WO2019236320A1 (en) 2018-06-08 2019-12-12 Globalwafers Co., Ltd. Method for transfer of a thin layer of silicon
US10943813B2 (en) * 2018-07-13 2021-03-09 Globalwafers Co., Ltd. Radio frequency silicon on insulator wafer platform with superior performance, stability, and manufacturability
EP4315398A4 (en) 2021-03-31 2025-03-05 Adeia Semiconductor Bonding Technologies Inc. DIRECT ADHESION AND REMOVING A CARRIER
US11798802B2 (en) * 2022-02-11 2023-10-24 Globalwafers Co., Ltd. Methods for stripping and cleaning semiconductor structures

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4824698A (en) * 1987-12-23 1989-04-25 General Electric Company High temperature annealing to improve SIMOX characteristics
JP2617798B2 (ja) 1989-09-22 1997-06-04 三菱電機株式会社 積層型半導体装置およびその製造方法
JPH07106512A (ja) 1993-10-04 1995-04-21 Sharp Corp 分子イオン注入を用いたｓｉｍｏｘ処理方法
US5478758A (en) 1994-06-03 1995-12-26 At&T Corp. Method of making a getterer for multi-layer wafers
JP3729955B2 (ja) * 1996-01-19 2005-12-21 株式会社半導体エネルギー研究所 半導体装置の作製方法
JPH09260288A (ja) * 1996-01-19 1997-10-03 Semiconductor Energy Lab Co Ltd 半導体装置及びその作製方法
US5888858A (en) 1996-01-20 1999-03-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and fabrication method thereof
US6033974A (en) 1997-05-12 2000-03-07 Silicon Genesis Corporation Method for controlled cleaving process
US6548382B1 (en) * 1997-07-18 2003-04-15 Silicon Genesis Corporation Gettering technique for wafers made using a controlled cleaving process
JPH1167778A (ja) * 1997-08-19 1999-03-09 Sumitomo Metal Ind Ltd Ｓｏｉ半導体ウエーハの製造方法
US7256104B2 (en) * 2003-05-21 2007-08-14 Canon Kabushiki Kaisha Substrate manufacturing method and substrate processing apparatus
US7294561B2 (en) 2003-08-14 2007-11-13 Ibis Technology Corporation Internal gettering in SIMOX SOI silicon substrates
US7084048B2 (en) * 2004-05-07 2006-08-01 Memc Electronic Materials, Inc. Process for metallic contamination reduction in silicon wafers
JP2010508676A (ja) * 2006-11-02 2010-03-18 アイメック 半導体デバイス層からの不純物の除去

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SG191966A1 (en) 2013-08-30
JP2014508405A (ja) 2014-04-03
EP2671247B1 (en) 2015-07-22
TW201250838A (en) 2012-12-16
WO2012106210A3 (en) 2012-11-01
MY166803A (en) 2018-07-23
KR20140018872A (ko) 2014-02-13
US20130168836A1 (en) 2013-07-04
CN103339713B (zh) 2016-06-15
CN103339713A (zh) 2013-10-02
US8796116B2 (en) 2014-08-05
WO2012106210A2 (en) 2012-08-09
KR101871534B1 (ko) 2018-06-26
US20130168802A1 (en) 2013-07-04
EP2671247A2 (en) 2013-12-11
US20120193753A1 (en) 2012-08-02

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