JP5968046B2 - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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Publication number
JP5968046B2
JP5968046B2 JP2012100634A JP2012100634A JP5968046B2 JP 5968046 B2 JP5968046 B2 JP 5968046B2 JP 2012100634 A JP2012100634 A JP 2012100634A JP 2012100634 A JP2012100634 A JP 2012100634A JP 5968046 B2 JP5968046 B2 JP 5968046B2
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JP
Japan
Prior art keywords
semiconductor chip
base plate
insulating substrate
solder
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2012100634A
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English (en)
Japanese (ja)
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JP2013229457A5 (https=
JP2013229457A (ja
Inventor
卓 楠
卓 楠
健嗣 大津
健嗣 大津
荒木　健
健 荒木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2012100634A priority Critical patent/JP5968046B2/ja
Publication of JP2013229457A publication Critical patent/JP2013229457A/ja
Publication of JP2013229457A5 publication Critical patent/JP2013229457A5/ja
Application granted granted Critical
Publication of JP5968046B2 publication Critical patent/JP5968046B2/ja
Expired - Fee Related legal-status Critical Current
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H10W72/5475—Dispositions of multiple bond wires multiple bond wires connected to common bond pads at both ends of the wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/926—Multiple bond pads having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips

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  • Die Bonding (AREA)
JP2012100634A 2012-04-26 2012-04-26 半導体装置および半導体装置の製造方法 Expired - Fee Related JP5968046B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2012100634A JP5968046B2 (ja) 2012-04-26 2012-04-26 半導体装置および半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012100634A JP5968046B2 (ja) 2012-04-26 2012-04-26 半導体装置および半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2013229457A JP2013229457A (ja) 2013-11-07
JP2013229457A5 JP2013229457A5 (https=) 2014-12-25
JP5968046B2 true JP5968046B2 (ja) 2016-08-10

Family

ID=49676805

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012100634A Expired - Fee Related JP5968046B2 (ja) 2012-04-26 2012-04-26 半導体装置および半導体装置の製造方法

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Country Link
JP (1) JP5968046B2 (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6265693B2 (ja) * 2013-11-12 2018-01-24 三菱電機株式会社 半導体装置およびその製造方法
JP2015216160A (ja) * 2014-05-08 2015-12-03 三菱電機株式会社 電力用半導体装置および電力用半導体装置の製造方法
EP3144986A4 (en) * 2014-05-16 2017-11-22 National Institute of Advanced Industrial Science and Technology Thermoelectric conversion element and thermoelectric conversion module
JP2018098219A (ja) * 2015-03-18 2018-06-21 株式会社日立製作所 半導体装置及びその製造方法。
JP6917127B2 (ja) * 2016-08-23 2021-08-11 ローム株式会社 半導体装置及びパワーモジュール
DE102016118784A1 (de) 2016-10-04 2018-04-05 Infineon Technologies Ag Chipträger, konfiguriert zur delaminierungsfreien Kapselung und stabilen Sinterung
JP6991950B2 (ja) * 2018-09-26 2022-01-13 日立Astemo株式会社 パワーモジュール
CN114256162A (zh) * 2020-09-23 2022-03-29 世界先进积体电路股份有限公司 芯片结构及电子装置
JP7761181B1 (ja) * 2024-08-02 2025-10-28 三菱電機株式会社 半導体装置及び半導体装置の製造方法
WO2026028484A1 (ja) * 2024-08-02 2026-02-05 三菱電機株式会社 半導体装置及び半導体装置の製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4904767B2 (ja) * 2005-10-17 2012-03-28 富士電機株式会社 半導体装置
JP2011029472A (ja) * 2009-07-28 2011-02-10 Hitachi Metals Ltd 接合材料及びこれを用いた半導体の実装方法並びに半導体装置

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Publication number Publication date
JP2013229457A (ja) 2013-11-07

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