WO2010047010A1 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
WO2010047010A1
WO2010047010A1 PCT/JP2009/002680 JP2009002680W WO2010047010A1 WO 2010047010 A1 WO2010047010 A1 WO 2010047010A1 JP 2009002680 W JP2009002680 W JP 2009002680W WO 2010047010 A1 WO2010047010 A1 WO 2010047010A1
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Prior art keywords
solder
die pad
semiconductor device
layer
solder material
Prior art date
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PCT/JP2009/002680
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English (en)
French (fr)
Inventor
松尾隆広
古澤彰男
酒谷茂昭
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パナソニック株式会社
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Publication date
Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Priority to CN200980100250A priority Critical patent/CN101790780A/zh
Priority to EP09807568A priority patent/EP2343734A1/en
Priority to US12/711,628 priority patent/US20100148367A1/en
Publication of WO2010047010A1 publication Critical patent/WO2010047010A1/ja

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    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
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Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof.
  • a semiconductor device used for a power supply unit of an electronic device such as a TV receiver generally includes a die pad made of metal and a semiconductor element (semiconductor chip) fixed on the die pad via a solder material. Has a configuration.
  • a spherical solder material is arranged on a heated die pad, and the arranged solder material is spread on the die pad and melted, and a semiconductor element is formed on the solder material in a molten state. Press. Thereafter, the semiconductor element is fixed on the die pad with a solder material by cooling (see, for example, Patent Document 1).
  • solder material of tin (Sn) -silver (Ag) -copper (Cu)
  • the melting point is as low as 220 ° C. Because the solder material is remelted due to heat when mounted on the semiconductor, and the molten solder material flows into the semiconductor element and causes a short circuit, conventional lead-free solder can be used as a fixing material between the die pad and the semiconductor element. There wasn't.
  • An object of the present invention is to solve the above-described conventional problems and to stably perform soldering of a semiconductor element on a die pad.
  • the present invention uses a solder material having a hardness higher than that of a solder bonding layer formed on a die pad to form a recess (concave portion) in the solder bonding layer. It is set as the structure which fills a part of solder material in the formed hollow part.
  • a semiconductor device includes a die pad made of a metal having a first solder joint layer formed on a surface thereof, and a solder material mainly composed of bismuth on the first solder joint layer of the die pad.
  • the first solder joint layer is made of a material softer than the solder material, and a recess portion formed by pressing the solder material is formed in a part of the first solder joint layer. The solder material is partially filled in the recess.
  • the first solder joint layer formed on the die pad is made of a material softer than the solder material mainly composed of bismuth. Therefore, the solder material is used as the first solder joint layer.
  • a recessed portion that is recessed toward the die pad can be formed in a part of the first solder joint layer.
  • the solder material is filled in the recess, so that the joint area between the first solder joint layer on the die pad and the solder material increases.
  • the connection strength between the die pad and the solder material is enhanced, the soldering of the semiconductor element onto the die pad is stabilized.
  • the first solder joint layer is preferably made of silver or a metal containing silver as a main component.
  • the solder material preferably contains bismuth, copper and germanium.
  • the die pad is preferably made of copper or a metal mainly composed of copper.
  • an opening from which the die pad is exposed is formed in the recess of the first solder joint layer, and the solder material is in contact with the surface of the die pad through the formed opening.
  • solder material has entered between the die pad and the first solder joint layer in the outer peripheral portion of the opening.
  • a second solder joint layer is formed on the surface of the semiconductor element facing the solder material, and the second solder joint layer is made of silver or a metal containing silver as a main component. It is preferable.
  • an adhesive layer, an intermediate bonding layer, and a barrier layer are sequentially formed between the semiconductor element and the second solder bonding layer from the semiconductor element toward the second solder bonding layer.
  • the adhesive layer is made of chromium
  • the intermediate bonding layer is made of an alloy of nickel and chromium
  • the barrier layer is made of nickel.
  • the method of manufacturing a semiconductor device includes a step of forming a recess in the first solder joint layer by pressing a spherical solder material on the first solder joint layer formed on the surface of the die pad. (A) and after the step (a), the step (b) of spreading the solder material on the first solder joint layer and the step (b) after the solder material spread on the first solder joint layer And a step (c) of pressing the semiconductor element.
  • the method for manufacturing a semiconductor device of the present invention preferably further includes a step (d) of heating the die pad before the step (a).
  • an opening exposing the die pad is formed in the recess formed in the first solder joint layer, and solder is formed through the formed opening. It is preferred that the material is in contact with the surface of the die pad.
  • the bonding area between the first solder bonding layer formed on the die pad and the solder material is increased, so that the connection strength between the die pad and the solder material is enhanced. Therefore, soldering of the semiconductor element onto the die pad is stabilized.
  • FIG. 1 is a perspective view showing a semiconductor device according to an embodiment of the present invention.
  • FIG. 2 is a plan view showing a semiconductor device according to an embodiment of the present invention.
  • 3 is a cross-sectional view taken along line III-III in FIG.
  • FIG. 4 is a partially enlarged sectional view showing a region IV of FIG.
  • FIG. 5 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 6 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 7 is a partially enlarged sectional view showing a region VII in FIG. 8 is a partially enlarged cross-sectional view showing a region VII of FIG. 6 following FIG.
  • FIG. 9 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 10 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 11 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 1 shows a semiconductor device according to an embodiment of the present invention, for example, a semiconductor device used for a power supply unit of a TV receiver.
  • FIG. 2 shows a planar configuration in which the sealing resin portion is omitted.
  • a current of about several tens of amperes to one hundred amperes flows.
  • the thickness is made of sufficiently thick copper (Cu), and a plurality of external leads 1 and a plurality of A lead frame in which the internal lead 2, the die pad 3, and the heat radiation part 4 are formed is used.
  • the heat dissipating part 4 is integrally formed on the opposite side of the die pad 3 from the external lead 1. Further, the external lead 1 and the internal lead 2 are formed integrally with each other, and one of the plurality of external leads 1 and the plurality of internal leads 2 is formed integrally with the die pad 3.
  • a semiconductor element (semiconductor chip) 5 is mounted on the die pad 3. Between the electrode 6 formed on the semiconductor element 5 and the internal lead 2 not connected to the die pad 3, for example, aluminum They are electrically connected by a wire 7 made of (Al).
  • the semiconductor element 5, the wire 7, the internal lead 2, and the die pad 3 are covered with a sealing resin portion 8 (not shown in FIG. 2).
  • a screw hole 4a is formed in the heat dissipating part 4, and if the screw hole 4a is fixed to a heat dissipating mechanism (not shown) of the power source part with a screw, the heat generated by the semiconductor element 5 is transferred to the die pad 3, Heat can be radiated to the heat radiating mechanism through the heat radiating portion 4 and the screw.
  • the semiconductor element 5 is fixed to the die pad 3 with a solder material 9.
  • an active layer 10 made of copper having a thickness of, for example, about 0.1 ⁇ m to 0.4 ⁇ m is provided on the surface of the die pad 3 by a vacuum deposition method or a sputtering method. It has been.
  • the active layer 10 made of copper is handled as the die pad 3.
  • copper was used for the die pad 3 including the external lead 1 and the internal lead 2, it is not limited only to copper, but may be an alloy containing silver (Ag) or cobalt (Co) in addition to copper.
  • a first solder bonding layer 11 made of silver (Ag) having a thickness of about 1 ⁇ m to 4 ⁇ m formed by plating is provided on the active layer 10.
  • the die pad 3 and the active solder layer 11 are activated.
  • the three-layer structure of the layer 10 and the first solder joint layer 11 is handled.
  • the lower part of the semiconductor element 5 is a semiconductor substrate made of, for example, silicon (Si), and the lower surface of the semiconductor substrate is bonded to chromium (Cr) with a thickness of about 0.05 ⁇ m by vacuum deposition or sputtering.
  • a second solder joint layer 15 made of silver by vacuum deposition or plating and having a thickness of about 0.5 ⁇ m to 5 ⁇ m is formed. That is, the back electrode 16 of the semiconductor element 5 is formed by the adhesive layer 12, the intermediate bonding layer 13, the barrier layer 14, and the second solder bonding layer 15.
  • silver was used for the 1st solder joint layer 11 and the 2nd solder joint layer 15, it is not restricted only to silver, It is an alloy containing cobalt (Co) or copper (Cu) in addition to silver. Also good.
  • the adhesive layer 12 may be an alloy containing chromium as a main component
  • the intermediate bonding layer 13 may be an alloy containing nickel-chromium alloy as a main component
  • the barrier layer 14 may be an alloy containing nickel as a main component.
  • solder material 9 is interposed, and the semiconductor element 5 is mounted and fixed on the die pad 3 by the solder 9 material.
  • Reference numeral 9a shown in FIG. 4 indicates a diffusion float of silver diffused into the solder material 9 from the first solder joint layer 11 and the second solder joint layer 15 both made of silver.
  • the hardness of the solder material 9 is set higher than the hardness of the first solder joint layer 11.
  • a depression 11 a that is pressed by the material 9 is formed.
  • an opening 11b exposing the lower active layer 10, that is, the die pad 3, is formed in the lower portion of the recess 11a. Accordingly, a part of the lower portion of the solder material 9 is filled in the recess 11a, and the solder material 9 enters between the die pad 3 and the first solder joint layer 11 in the outer peripheral portion of the opening 11b. Yes.
  • the solder material 9 is filled in the recess 11a, the bonding area between the first solder bonding layer 11 and the solder material 9 on the die pad 3 increases.
  • the connection strength between the first solder joint layer 11 and the solder material 9 is enhanced. As a result, the soldering of the semiconductor element 5 onto the die pad 3 is stabilized.
  • 5 to 11 show cross-sectional structures in the order of steps of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • a die pad 3 having an active layer 10 (not shown) and a first solder joint layer 11 formed on the surface in advance is placed on a heat block 17, and then a reducing atmosphere, for example, Heat to about 310 ° C. in a green gas (a mixed gas of nitrogen (N 2 ) and hydrogen (H 2 )) or in a non-oxidizing atmosphere, for example, a nitrogen (N 2 ) atmosphere.
  • a reducing atmosphere for example, Heat to about 310 ° C. in a green gas (a mixed gas of nitrogen (N 2 ) and hydrogen (H 2 )) or in a non-oxidizing atmosphere, for example, a nitrogen (N 2 ) atmosphere.
  • solder material 9A is pressed onto the solder joint layer 11 of the die pad 3 heated in a reducing atmosphere or a non-oxidizing atmosphere.
  • the solder material 9A has bismuth (Bi) as a main component, is composed of copper (Cu), germanium (Ge), and inevitable components, and has a melting point of about 270 ° C.
  • the solder material 9A contains about 98% of bismuth (hereinafter referred to as% by weight), about 2% of copper, and about 0.06% of germanium. Is made of, for example, iron (Fe), nickel (Ni), lead (Pb), zinc (Zn), aluminum (Al), cadmium (Cd), or arsenic (As), each containing less than about 0.01% Yes.
  • the Mohs hardness of the solder material 9A is about 2.5, which is higher than about 2.0 of the Mohs hardness of the first solder joint layer 11 therebelow.
  • FIG. 7 which is a partially enlarged view of the region VII in FIG. 6, when the spherical solder material 9A is pressed against the first solder joint layer 11, the first solder joint layer softer than the solder material 9A. 11 is formed with a recess 11a.
  • solder material 9A when the solder material 9A is pressed, an opening 11b is formed in a part of the lower portion of the recess 11a, and eventually the active layer 10 of the die pad 3 is formed through the formed opening 11b.
  • a part of the solder material 9A enters between the first solder joint layer 11 and the first solder joint layer 11. That is, the solder material 9A is also applied to the region outside the opening 11b between the active layer 10 and the first solder bonding layer 11 instead of the first solder bonding layer 11 located around the opening 11b. In this state, the active layer 10 and a part of the solder material 9A are joined.
  • the lower part of the solder material 9A is not only filled into the recess 11a, but is also bonded to the active layer 10 of the die pad 3 in a wide range (outside region of the opening 11b). Therefore, the strength at which the lower part of the solder material 9A is bonded to the die pad 3 is increased.
  • the opening 11b is formed below the solder material 9A in the first solder joint layer 11, and the solder material 9A extends to the outside of the opening 11b, and in this state, the active layer 10 of the die pad 3
  • the solder material 9A is mainly composed of bismuth
  • the silver constituting the first solder joint layer 11 is used. Is considered to be due to diffusion in bismuth.
  • the diffusion of silver into bismuth means that the silver diffused from the first solder joint layer 11 and the second solder joint layer 15 is diffused into the solder material 9 as shown in FIG. It is considered that the possibility is high from the formation of 9a.
  • the spherical solder material 9 ⁇ / b> A is spread by the presser pin 18 in a state where the lower part of the solder material 9 ⁇ / b> A is joined to the die pad 3 in the heating state of the reducing atmosphere or the non-oxidizing atmosphere.
  • the solder material 9 ⁇ / b> A is melted in a gentle convex shape in a heating state in a reducing atmosphere or a non-oxidizing atmosphere.
  • the semiconductor element 5 is pressed onto the solder material 9A in a heating state of a reducing atmosphere or a non-oxidizing atmosphere. Thereafter, the temperature is lowered in this state to solidify the solder material 9, and the semiconductor device having the configuration shown in FIG. 4 is obtained.
  • a back electrode 16 including the adhesive layer 12, the intermediate bonding layer 13, the barrier layer 14, and the second solder bonding layer 15 having the above-described configuration is formed in advance.
  • nickel is used for the barrier layer 14 constituting the back electrode 16 since the second solder joint layer 15 made of silver is interposed between the back electrode 16 and the solder material 9, In the step shown in FIG. 11, there is no possibility that nickel ions diffuse into the solder material 9 and raise its melting temperature.
  • the back electrode 16 is not limited to the above-described configuration, and gold (Au) -germanium (Ge), gold (Au) -germanium (Ge) -antimony (Sb), or titanium (Ti) -nickel (Ni)-
  • a back electrode such as silver (Ag) that can generally be used in a semiconductor device.
  • the first solder joint layer 11 formed on the surface of the die pad 3 is made of a material softer than the solder material 9 containing bismuth as a main component, and the solder By pressing the material 9 against the first solder joint layer 11, a depression 11 a can be formed in a part of the first solder joint layer 11 toward the die pad 3.
  • the solder material 9 can be filled in the hollow portion 11a, the bonding area between the first solder joint layer 11 and the solder material 9 on the die pad 3 increases, so that the space between the solder material 9 and the die pad 3 is increased.
  • the connection strength is strengthened. As a result, the soldering of the semiconductor element 5 onto the die pad 3 is stabilized.
  • the connection strength between the die pad and the solder material is strengthened, the soldering of the semiconductor element onto the die pad is stable, and particularly in an electronic device that becomes high temperature during operation. It is useful for a semiconductor device to be incorporated, a manufacturing method thereof, and the like.

Abstract

　半導体装置は、表面に第１のはんだ接合層が形成された金属からなるダイパッド（３）と、該ダイパッド（３）における第１のはんだ接合層１１の上に、ビスマスを主成分とするはんだ材（９）により固着された半導体素子（５）とを有している。第１のはんだ接合層（１１）は、はんだ材（９）よりも軟らかい材料からなり、第１のはんだ接合層（１１）の一部には、はんだ材（９）が押圧されてなる窪み部（１１ａ）が形成され、はんだ材（９）の一部は、窪み部（１１ａ）に充填されている。

Description

半導体装置及びその製造方法
　本発明は、半導体装置及びその製造方法に関する。
　例えば、ＴＶ受像機等の電子機器の電源部に利用される半導体装置は、一般に金属からなるダイパッドと、該ダイパッドの上にはんだ材を介して固着された半導体素子（半導体チップ）とを備えた構成を持つ。
　このような半導体装置は、まず、加熱したダイパッドの上に球状のはんだ材を配置し、配置されたはんだ材をダイパッドの上に押し広げると共に溶融させ、溶融状態にあるはんだ材の上に半導体素子を押し付ける。その後冷却することにより、半導体素子をはんだ材でダイパッド上に固着することにより得られる（例えば、特許文献１を参照。）。
特開２００２－１５６５６１号公報
　近年、はんだ材の鉛フリー化が推進されているが、半導体装置、特にパワー系半導体装置において、ダイパッドと半導体素子とを固着しているはんだ材はその代替材料がなく、現在でも鉛を主成分とするはんだ材を使用しており、早急な鉛フリー化が要望されている。
　しかしながら、従来の錫（Ｓｎ）－銀（Ａｇ）－銅（Ｃｕ）系の鉛フリーはんだ材でダイパッドと半導体素子を固着させた場合、その融点が２２０℃と低いため、半導体装置をプリント配線板に実装する時の熱により、はんだ材が再溶融し、その溶融はんだ材が半導体素子上に流れ込みショートを引き起こすため、従来の鉛フリーはんだをダイパッドと半導体素子との固着材として採用することができなかった。
　そこで、溶融温度が高い鉛フリーはんだ材が研究されているものの、今度は溶融温度が高いことから、ダイパッド上への半導体素子のはんだ付けが安定しないという問題が発生する。
　具体的には、はんだ材の上には半導体素子が実装されるため、溶融温度が高いはんだ材であっても、実質上は半導体素子が熱破壊されない程度の温度にまでしか加熱することができず、その結果、半導体素子のダイパッド上へのはんだ付けを安定して行うことができない。
　本発明は、前記従来に問題を解決し、ダイパッド上への半導体素子のはんだ付けを安定して行えるようにすることを目的とする。
　前記の目的を達成するため、本発明は、半導体装置を、ダイパッド上に形成されるはんだ接合層よりも硬度が高いはんだ材を用いることにより、はんだ接合層に窪み部（凹部）を形成し、形成された窪み部にはんだ材の一部を充填する構成とする。
　具体的に、本発明に係る半導体装置は、表面に第１のはんだ接合層が形成された金属からなるダイパッドと、ダイパッドにおける第１のはんだ接合層の上に、ビスマスを主成分とするはんだ材により固着された半導体素子とを備え、第１のはんだ接合層は、はんだ材よりも軟らかい材料からなり、第１のはんだ接合層の一部には、はんだ材が押圧されてなる窪み部が形成され、はんだ材の一部は、窪み部に充填されていることを特徴とする。
　本発明の半導体装置によると、ダイパッド上に形成される第１のはんだ接合層に、ビスマスを主成分とするはんだ材よりも軟らかい材料を用いているため、はんだ材を第１のはんだ接合層に押し付けることにより、第１のはんだ接合層の一部にダイパッド側に窪む窪み部を形成することができる。これにより、窪み部にはんだ材が充填されるため、ダイパッド上の第１のはんだ接合層とはんだ材との接合面積が増大する。その結果、ダイパッドとはんだ材との間の接続強度が強化されるので、ダイパッド上への半導体素子のはんだ付けが安定する。
　本発明の半導体装置において、第１のはんだ接合層は、銀又は銀を主成分とする金属からなることが好ましい。
　本発明の半導体装置において、はんだ材は、ビスマス、銅及びゲルマニウムを含むことが好ましい。
　本発明の半導体装置において、ダイパッドは、銅又は銅を主成分とする金属からなることが好ましい。
　本発明の半導体装置において、第１のはんだ接合層の窪み部には、ダイパッドが露出する開口部が形成され、形成された開口部を介してはんだ材がダイパッドの表面と接していることが好ましい。
　この場合に、開口部の外周部分におけるダイパッドと第１のはんだ接合層との間には、はんだ材が進入していることが好ましい。
　本発明の半導体装置において、半導体素子におけるはんだ材と対向する面上には、第２のはんだ接合層が形成されており、第２のはんだ接合層は銀又は銀を主成分とする金属からなることが好ましい。
　この場合に、半導体素子と第２のはんだ接合層との間には、半導体素子から第２のはんだ接合層に向かって、接着層、中間接合層及びバリア層が順次形成されていることが好ましい。
　また、この場合に、接着層はクロムからなり、中間接合層はニッケルとクロムとの合金からなり、バリア層はニッケルからなることが好ましい。
　本発明に係る半導体装置の製造方法は、ダイパッドの表面に形成された第１のはんだ接合層の上に、球状のはんだ材を押し付けることにより、第１のはんだ接合層に窪み部を形成する工程（ａ）と、工程（ａ）よりも後に、はんだ材を第１のはんだ接合層の上に押し広げる工程（ｂ）と、工程（ｂ）よりも後に、押し広げられたはんだ材の上に半導体素子を押し付ける工程（ｃ）とを備えていることを特徴とする。
　本発明の半導体装置の製造方法は、工程（ａ）よりも前に、ダイパッドを加熱する工程（ｄ）をさらに備えていることが好ましい。
　本発明の半導体装置の製造方法は、工程（ａ）において、第１のはんだ接合層に形成された窪み部には、ダイパッドを露出する開口部が形成され、形成された開口部を介してはんだ材がダイパッドの表面と接触することが好ましい。
　本発明に係る半導体装置及びその製造方法によると、ダイパッド上に形成された第１のはんだ接合層とはんだ材との接合面積が増大するため、ダイパッドとはんだ材との間の接続強度が強化されるので、ダイパッド上への半導体素子のはんだ付けが安定する。
図１は本発明の一実施形態に係る半導体装置を示す斜視図である。 図２は本発明の一実施形態に係る半導体装置を示す平面図である。 図３は図２のIII－III線における断面図である。 図４は図３の領域IVを示す部分拡大断面図である。 図５は本発明の一実施形態に係る半導体装置の製造方法の一工程を示す断面図である。 図６は本発明の一実施形態に係る半導体装置の製造方法の一工程を示す断面図である。 図７は図６の領域ＶIIを示す部分拡大断面図である。 図８は図７に続く図６の領域ＶIIを示す部分拡大断面図である。 図９は本発明の一実施形態に係る半導体装置の製造方法の一工程を示す断面図である。 図１０は本発明の一実施形態に係る半導体装置の製造方法の一工程を示す断面図である。 図１１は本発明の一実施形態に係る半導体装置の製造方法の一工程を示す断面図である。
　（一実施形態）
　本発明の一実施形態について図面を用いて説明する。
　図１は本発明の一実施形態に係る半導体装置であって、例えばＴＶ受像機の電源部に利用される半導体装置を示している。また、図２は封止樹脂部を省略した平面構成を示している。電源部に用いられる半導体装置は、数十アンペアから百アンペア程度の電流が流れる。この電流に伴う発熱により半導体素子が破壊されるのを防止するため、図１及び図２に示すように、肉厚が十分に厚い銅（Ｃｕ）からなり、且つ複数の外部リード１、複数の内部リード２、ダイパッド３及び放熱部４が形成されたリードフレームを用いている。放熱部４は、ダイパッド３における外部リード１と反対側に一体に形成されている。また、外部リード１と内部リード２とはそれぞれ一体に形成され、且つ複数の外部リード１及び複数の内部リード２のうちの１つは、ダイパッド３と一体に形成されている。
　図２に示すように、ダイパッド３の上には半導体素子（半導体チップ）５が実装され、半導体素子５に形成された電極６と、ダイパッド３と接続されない内部リード２との間は、例えばアルミニウム（Ａｌ）からなるワイヤ７によって電気的に接続されている。
　半導体素子５、ワイヤ７、内部リード２及びダイパッド３は、封止樹脂部８（図２では省略）で覆われている。
　なお、放熱部４には、ねじ止め孔４ａが形成されており、該ねじ止め孔４ａをねじによって電源部の放熱機構（図示せず）に固持すれば、半導体素子５の発熱をダイパッド３、放熱部４及びねじを介して放熱機構に放熱させることができる。
　図３に示すように、半導体素子５は、はんだ材９によりダイパッド３に固着される。具体的には、図４に示すように、ダイパッド３の表面上には、真空蒸着法又はスパッタ法等により、例えば厚さが０．１μｍ～０．４μｍ程度の銅からなる活性層１０が設けられている。本実施形態においては、銅からなる活性層１０も含めてダイパッド３として取り扱う。なお、外部リード１及び内部リード２を含めダイパッド３には銅を用いたが、銅のみに限られず、銅の他に銀（Ａｇ）又はコバルト（Ｃｏ）を含む合金であってもよい。
　活性層１０の上には、鍍金により形成された厚さが１μｍ～４μｍ程度の銀（Ａｇ）からなる第１のはんだ接合層１１が設けられており、半導体装置の製造時には、ダイパッド３、活性層１０及び第１のはんだ接合層１１の３層構造で扱われる。
　半導体素子５の下部は、例えばシリコン（Ｓｉ）からなる半導体基板であり、該半導体基板の下面には、真空蒸着法又はスパッタ法により、厚さが０．０５μｍ程度のクロム（Ｃｒ）からなる接着層１２、厚さが０．０５μｍ程度のニッケル（Ｎｉ）－クロム（Ｃｒ）合金からなる中間接合層１３及び厚さが０．３μｍ程度のニッケル（Ｎｉ）からなるバリア層１４が順次形成され、該バリア層１４の下面には、真空蒸着又は鍍金による銀からなり、厚さが０．５μｍ～５μｍ程度の第２のはんだ接合層１５が形成されている。すなわち、これら接着層１２、中間接合層１３、バリア層１４及び第２のはんだ接合層１５により、半導体素子５の裏面電極１６が形成されている。
　なお、第１のはんだ接合層１１及び第２のはんだ接合層１５には銀を用いたが、銀のみに限られず、銀の他にコバルト（Ｃｏ）又は銅（Ｃｕ）を含む合金であってもよい。
　また、接着層１２はクロムを主成分とする合金でもよく、中間接合層１３はニッケル－クロム合金を主成分とする合金でもよく、バリア層１４は、ニッケルを主成分とする合金でもよい。
　以上のような構成を持つダイパッド３及び半導体素子５において、ダイパッド３上の第１のはんだ接合層１１と、半導体素子５の裏面電極１６を構成する第２のはんだ接合層１５との間に、はんだ材９が介在し、該はんだ９材によってダイパッド３の上に半導体素子５が実装されて固着される。なお、図４に示した符号９ａは、共に銀からなる第１のはんだ接合層１１及び第２のはんだ接合層１５からはんだ材９の内部に拡散した銀の拡散フロートを示している。
　図４に示すように、本実施形態においては、はんだ材９の硬度を第１のはんだ接合層１１の硬度よりも高く設定しているため、製造時に第１のはんだ接合層１１には、はんだ材９によって押圧されてなる窪み部１１ａが形成されている。さらに、窪み部１１ａの下部には、その下側の活性層１０、すなわちダイパッド３を露出する開口部１１ｂが形成されている。従って、はんだ材９の下部の一部は、窪み部１１ａに充填されると共に、開口部１１ｂの外周部分におけるダイパッド３と第１のはんだ接合層１１との間に、はんだ材９が進入している。
　このように、本実施形態に係る半導体装置は、窪み部１１ａにはんだ材９が充填されているため、ダイパッド３上の第１のはんだ接合層１１とはんだ材９との接合面積が増大するので、第１のはんだ接合層１１とはんだ材９との接続強度が強化される。その結果、ダイパッド３上への半導体素子５のはんだ付けが安定する。
　以下、前記のように構成された半導体装置の製造方法について図面を参照しながら説明する。
　図５～図１１は本発明の第１の実施形態に係る半導体装置の製造方法の工程順の断面構成を示している。
　まず、図５に示すように、あらかじめ表面に活性層１０（図示せず）及び第１のはんだ接合層１１が形成されたダイパッド３をヒートブロック１７の上に配置し、その後、還元雰囲気、例えばグリーンガス（窒素（Ｎ２）と水素（Ｈ２）との混合ガス)、又は非酸化雰囲気、例えば窒素（Ｎ２）雰囲気で、約３１０℃に加熱する。
　次に、図６に示すように、還元雰囲気又は非酸化雰囲気で加熱されているダイパッド３のはんだ接合層１１の上に、球状のはんだ材９Ａを押し付ける。はんだ材９Ａは、ビスマス（Ｂｉ）を主成分とし、銅（Ｃｕ）及びゲルマニウム（Ｇｅ）と不可避成分により構成され、融点は約２７０℃である。ここで、はんだ材９Ａには、ビスマスが約９８％（以下、重量％を％と表示する。）、銅が約２％、及びゲルマニウムが約０．０６％含まれており、また、不可避成分は、例えば鉄（Ｆｅ）、ニッケル（Ｎｉ）、鉛（Ｐｂ）、亜鉛（Ｚｎ）、アルミニウム（Ａｌ）、カドミウム（Ｃｄ）又は砒素（Ａｓ）からなり、それぞれ約０．０１％未満含まれている。
　はんだ材９Ａのモース硬度は約２．５であり、その下の第１のはんだ接合層１１のモース硬度の約２．０よりも高い。
　従って、図６の領域ＶIIの部分拡大図である図７に示すように、球状のはんだ材９Ａを、第１のはんだ接合層１１に押し付けると、はんだ材９Ａよりも軟らかい第１のはんだ接合層１１には窪み部１１ａが形成される。
　さらに、図８に示すように、はんだ材９Ａを押し付けると、窪み部１１ａの下部の一部に開口部１１ｂが形成され、やがては、形成された開口部１１ｂを介してダイパッド３の活性層１０と第１のはんだ接合層１１との間にはんだ材９Ａの一部が進入する。すなわち、はんだ材９Ａが、開口部１１ｂの周囲に位置する第１のはんだ接合層１１の代わりに、活性層１０と第１のはんだ接合層１１との間の開口部１１ｂの外側の領域にも拡がり、この状態で活性層１０とはんだ材９Ａの一部とが接合される。
　このように、本実施形態においては、はんだ材９Ａの下部は窪み部１１ａに充填されるだけでなく、ダイパッド３の活性層１０に対しても広い範囲（開口部１１ｂの外側領域）で接合されるため、はんだ材９Ａの下部がダイパッド３と接合される強度が高くなる。
　なお、第１のはんだ接合層１１におけるはんだ材９Ａの下側に開口部１１ｂが形成されること、及びはんだ材９Ａが開口部１１ｂの外側にも拡がり、その状態でダイパッド３の活性層１０とはんだ材９Ａの一部が接合されることの理由は、未だ十分には明確となっていないが、はんだ材９Ａがビスマスを主成分とすることから、第１のはんだ接合層１１を構成する銀がビスマス中に拡散したことによると考えられる。銀がビスマス中に拡散することは、図４に示したように、第１のはんだ接合層１１及び第２のはんだ接合層１５からそれぞれ拡散した銀が、はんだ材９の内部に銀の拡散フロート９ａを形成することからも、その可能性が高いと考えられる。
　次に、図９に示すように、還元雰囲気又は非酸化雰囲気の加熱状態において、はんだ材９Ａの下部がダイパッド３と接合された状態で、押えピン１８によって球状のはんだ材９Ａを押し広げる。
　次に、図１０に示すように、還元雰囲気又は非酸化雰囲気の加熱状態において、はんだ材９Ａをなだらかな凸状に溶融させる。
　次に、図１１に示すように、還元雰囲気又は非酸化雰囲気の加熱状態において、はんだ材９Ａの上に、半導体素子５を押し付ける。その後、この状態で温度を下げてはんだ材９を固化させ、図４に示した構成の半導体装置を得る。なお、半導体素子５の裏面には、前述した構成を持つ接着層１２、中間接合層１３、バリア層１４及び第２のはんだ接合層１５からなる裏面電極１６があらかじめ形成されている。また、裏面電極１６を構成するバリア層１４にはニッケルを用いているが、裏面電極１６とはんだ材９との間には、銀からなる第２のはんだ接合層１５を介在させているため、図１１に示す工程において、ニッケルイオンがはんだ材９に拡散して、その溶融温度を上昇させてしまうおそれはない。
　また、裏面電極１６は、上述した構成に限られず、金（Ａｕ）－ゲルマニウム（Ｇｅ）、金（Ａｕ）－ゲルマニウム（Ｇｅ）－アンチモン（Ｓｂ）、又はチタン（Ｔｉ）－ニッケル（Ｎｉ）－銀（Ａｇ）等の、一般に半導体装置に使用できる裏面電極であれば同様の効果を示す。
　以上説明したように、本発明に係る半導体装置は、ダイパッド３の表面上に形成した第１のはんだ接合層１１を、ビスマスを主成分とするはんだ材９よりも軟らかい材料で構成し、該はんだ材９を第１のはんだ接合層１１に押し付けることにより、第１のはんだ接合層１１の一部に、ダイパッド３側へ窪み部１１ａを形成することができる。これにより、窪み部１１ａにはんだ材９を充填することができるため、ダイパッド３上の第１のはんだ接合層１１とはんだ材９の接合面積が増大するので、はんだ材９とダイパッド３との間の接続強度が強化される。その結果、ダイパッド３上への半導体素子５のはんだ付けが安定する。
　本発明に係る半導体装置及びその製造方法は、ダイパッドとはんだ材との間の接続強度が強化されるので、ダイパッド上への半導体素子のはんだ付けが安定し、特に動作時に高温となる電子機器に組み込まれる半導体装置及びその製造方法等に有用である。
１　　　外部リード
２　　　内部リード
３　　　ダイパッド
４　　　放熱部
４ａ　　ねじ止め孔
５　　　半導体素子
６　　　電極
７　　　ワイヤ
８　　　封止樹脂部
９　　　はんだ材
９Ａ　　はんだ材（球状のはんだ材）
９ａ　　拡散フロート
１０　　活性層
１１　　第１のはんだ接合層
１１ａ　窪み部
１１ｂ　開口部
１２　　接着層
１３　　中間接合層
１４　　バリア層
１５　　第２のはんだ接合層
１６　　裏面電極
１７　　ヒートブロック
１８　　押えピン

Claims (12)

  1. 　表面に第１のはんだ接合層が形成された金属からなるダイパッドと、
    　前記ダイパッドにおける前記第１のはんだ接合層の上に、ビスマスを主成分とするはんだ材により固着された半導体素子とを備え、
    　前記第１のはんだ接合層は、前記はんだ材よりも軟らかい材料からなり、
    　前記第１のはんだ接合層の一部には、前記はんだ材が押圧されてなる窪み部が形成され、前記はんだ材の一部は、前記窪み部に充填されている半導体装置。
  2. 　請求項１において、
    　前記第１のはんだ接合層は、銀又は銀を主成分とする金属からなる半導体装置。
  3. 　請求項１又は２において、
    　前記はんだ材は、ビスマス、銅及びゲルマニウムを含む半導体装置。
  4. 　請求項１～３のいずれか１項において、
    　前記ダイパッドは、銅又は銅を主成分とする金属からなる半導体装置。
  5. 　請求項１～４のいずれか１項において、
    　前記第１のはんだ接合層の前記窪み部には、前記ダイパッドが露出する開口部が形成され、形成された開口部を介して前記はんだ材が前記ダイパッドの表面と接している半導体装置。
  6. 　請求項５において、
    　前記開口部の外周部分における前記ダイパッドと前記第１のはんだ接合層との間には、前記はんだ材が進入している半導体装置。
  7. 　請求項１～６のいずれか１項において、
    　前記半導体素子における前記はんだ材と対向する面上には、第２のはんだ接合層が形成されており、前記第２のはんだ接合層は銀又は銀を主成分とする金属からなる半導体装置。
  8. 　請求項７において、
    　前記半導体素子と前記第２のはんだ接合層との間には、前記半導体素子から前記第２のはんだ接合層に向かって、接着層、中間接合層及びバリア層が順次形成されている半導体装置。
  9. 　請求項８において、
    　前記接着層はクロムからなり、前記中間接合層はニッケルとクロムとの合金からなり、前記バリア層はニッケルからなる半導体装置。
  10. 　請求項１～９のいずれか１項に記載の半導体装置の製造方法であって、
    　前記ダイパッドの表面に形成された前記第１のはんだ接合層の上に、球状の前記はんだ材を押し付けることにより、前記第１のはんだ接合層に窪み部を形成する工程（ａ）と、
    　前記工程（ａ）よりも後に、前記はんだ材を前記第１のはんだ接合層の上に押し広げる工程（ｂ）と、
    　前記工程（ｂ）よりも後に、押し広げられた前記はんだ材の上に前記半導体素子を押し付ける工程（ｃ）とを備えている半導体装置の製造方法。
  11. 　請求項１０において、
    　前記工程（ａ）よりも前に、前記ダイパッドを加熱する工程（ｄ）をさらに備えている半導体装置の製造方法。
  12. 　請求項１０又は１１において、
    　前記工程（ａ）において、前記第１のはんだ接合層に形成された窪み部には、前記ダイパッドを露出する開口部が形成され、形成された開口部を介して前記はんだ材が前記ダイパッドの表面と接触する半導体装置の製造方法。
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JP2017509489A (ja) 2014-02-20 2017-04-06 ハネウェル・インターナショナル・インコーポレーテッド 鉛フリーはんだ組成物
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