JP5968046B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
- Publication number
- JP5968046B2 JP5968046B2 JP2012100634A JP2012100634A JP5968046B2 JP 5968046 B2 JP5968046 B2 JP 5968046B2 JP 2012100634 A JP2012100634 A JP 2012100634A JP 2012100634 A JP2012100634 A JP 2012100634A JP 5968046 B2 JP5968046 B2 JP 5968046B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- base plate
- insulating substrate
- solder
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 128
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 229910000679 solder Inorganic materials 0.000 claims description 69
- 239000000758 substrate Substances 0.000 claims description 63
- 229910052709 silver Inorganic materials 0.000 claims description 62
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 58
- 239000004332 silver Substances 0.000 claims description 58
- 239000010931 gold Substances 0.000 claims description 35
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 20
- 229910052737 gold Inorganic materials 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 229910045601 alloy Inorganic materials 0.000 claims description 11
- 239000000956 alloy Substances 0.000 claims description 11
- 238000005304 joining Methods 0.000 claims description 10
- 238000005245 sintering Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- 229910002601 GaN Inorganic materials 0.000 claims description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- 239000010432 diamond Substances 0.000 claims description 3
- 229910003460 diamond Inorganic materials 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims 8
- 238000010030 laminating Methods 0.000 claims 2
- 239000000919 ceramic Substances 0.000 description 38
- 239000008188 pellet Substances 0.000 description 15
- 229910052802 copper Inorganic materials 0.000 description 13
- 239000010949 copper Substances 0.000 description 13
- 238000010586 diagram Methods 0.000 description 11
- 230000005012 migration Effects 0.000 description 11
- 238000013508 migration Methods 0.000 description 11
- 238000007747 plating Methods 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 6
- 230000017525 heat dissipation Effects 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 229910052787 antimony Inorganic materials 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- 238000002844 melting Methods 0.000 description 4
- 230000008018 melting Effects 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- 229910052725 zinc Inorganic materials 0.000 description 4
- 229910052763 palladium Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 238000005275 alloying Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8384—Sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Die Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012100634A JP5968046B2 (ja) | 2012-04-26 | 2012-04-26 | 半導体装置および半導体装置の製造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012100634A JP5968046B2 (ja) | 2012-04-26 | 2012-04-26 | 半導体装置および半導体装置の製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2013229457A JP2013229457A (ja) | 2013-11-07 |
| JP2013229457A5 JP2013229457A5 (enrdf_load_stackoverflow) | 2014-12-25 |
| JP5968046B2 true JP5968046B2 (ja) | 2016-08-10 |
Family
ID=49676805
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2012100634A Expired - Fee Related JP5968046B2 (ja) | 2012-04-26 | 2012-04-26 | 半導体装置および半導体装置の製造方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5968046B2 (enrdf_load_stackoverflow) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6265693B2 (ja) * | 2013-11-12 | 2018-01-24 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
| JP2015216160A (ja) * | 2014-05-08 | 2015-12-03 | 三菱電機株式会社 | 電力用半導体装置および電力用半導体装置の製造方法 |
| EP3144986A4 (en) * | 2014-05-16 | 2017-11-22 | National Institute of Advanced Industrial Science and Technology | Thermoelectric conversion element and thermoelectric conversion module |
| JP2018098219A (ja) * | 2015-03-18 | 2018-06-21 | 株式会社日立製作所 | 半導体装置及びその製造方法。 |
| JP6917127B2 (ja) * | 2016-08-23 | 2021-08-11 | ローム株式会社 | 半導体装置及びパワーモジュール |
| DE102016118784A1 (de) | 2016-10-04 | 2018-04-05 | Infineon Technologies Ag | Chipträger, konfiguriert zur delaminierungsfreien Kapselung und stabilen Sinterung |
| JP6991950B2 (ja) * | 2018-09-26 | 2022-01-13 | 日立Astemo株式会社 | パワーモジュール |
| CN114256162A (zh) * | 2020-09-23 | 2022-03-29 | 世界先进积体电路股份有限公司 | 芯片结构及电子装置 |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4904767B2 (ja) * | 2005-10-17 | 2012-03-28 | 富士電機株式会社 | 半導体装置 |
| JP2011029472A (ja) * | 2009-07-28 | 2011-02-10 | Hitachi Metals Ltd | 接合材料及びこれを用いた半導体の実装方法並びに半導体装置 |
-
2012
- 2012-04-26 JP JP2012100634A patent/JP5968046B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2013229457A (ja) | 2013-11-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5968046B2 (ja) | 半導体装置および半導体装置の製造方法 | |
| CN103035601B (zh) | 在烧结银层上包括扩散焊接层的半导体器件 | |
| US8643185B2 (en) | Semiconductor apparatus, manufacturing method of semiconductor apparatus, and joint material | |
| JP4262672B2 (ja) | 半導体装置およびその製造方法 | |
| TWI523724B (zh) | A bonding material, a method for producing the same, and a method of manufacturing the bonding structure | |
| KR101609495B1 (ko) | 반도체 장치 및 반도체 장치의 제조 방법 | |
| CN108475647B (zh) | 电力用半导体装置以及制造电力用半导体装置的方法 | |
| JP5578326B2 (ja) | リード部品及びその製造方法、並びに半導体パッケージ | |
| CN102017107A (zh) | 接合结构以及电子器件 | |
| JP2019067986A (ja) | 電力用半導体装置 | |
| JP2006066716A (ja) | 半導体装置 | |
| JP2005340268A (ja) | トランジスタパッケージ | |
| CN101790780A (zh) | 半导体装置及其制造方法 | |
| JP6972174B2 (ja) | 半導体装置および半導体装置の製造方法 | |
| CN102132390B (zh) | 接合结构体、接合材料及接合材料的制造方法 | |
| JP2011243752A (ja) | 半導体装置の製造方法、半導体内部接続部材および半導体内部接続部材群 | |
| JP2005129886A (ja) | 半導体装置およびその製造方法 | |
| JP2017103290A (ja) | 半導体装置およびその製造方法、パワーモジュール並びに車両 | |
| JP2009147123A (ja) | 半導体装置及びその製造方法 | |
| JP2005236019A (ja) | 半導体装置の製造方法 | |
| JP7320446B2 (ja) | 半導体装置およびその製造方法 | |
| TWI555125B (zh) | 功率模組封裝體的製造方法 | |
| JP6011410B2 (ja) | 半導体装置用接合体、パワーモジュール用基板及びパワーモジュール | |
| CN112951786A (zh) | 焊料材料、层结构及其形成方法、芯片封装及其形成方法、芯片布置及其形成方法 | |
| JP7582156B2 (ja) | 半導体装置及びその製造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20141107 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20141107 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20150924 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20151006 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20151119 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20160607 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20160705 |
|
| R151 | Written notification of patent or utility model registration |
Ref document number: 5968046 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |