JP5964511B2 - オフセットビア（ｖｉａｓ）を有する集積回路パッケージ - Google Patents

オフセットビア（ｖｉａｓ）を有する集積回路パッケージ Download PDF

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Publication number
JP5964511B2
JP5964511B2 JP2015520404A JP2015520404A JP5964511B2 JP 5964511 B2 JP5964511 B2 JP 5964511B2 JP 2015520404 A JP2015520404 A JP 2015520404A JP 2015520404 A JP2015520404 A JP 2015520404A JP 5964511 B2 JP5964511 B2 JP 5964511B2
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Prior art keywords
integrated circuit
semiconductor chip
center
insulating layer
vias
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JP2015525968A (ja
Inventor
ジャオイン スー マイケル
ジャオイン スー マイケル
レイ フー
レイ フー
クーヘンマイスター フランク
クーヘンマイスター フランク
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • H10W74/147—
    • H10W72/012—
    • H10W72/019—
    • H10W72/20—
    • H10W72/90—
    • H10W20/082—
    • H10W42/121—
    • H10W72/01235—
    • H10W72/01255—
    • H10W72/01935—
    • H10W72/0198—
    • H10W72/072—
    • H10W72/07236—
    • H10W72/227—
    • H10W72/234—
    • H10W72/237—
    • H10W72/241—
    • H10W72/242—
    • H10W72/244—
    • H10W72/247—
    • H10W72/248—
    • H10W72/252—
    • H10W72/29—
    • H10W72/926—
    • H10W72/934—
    • H10W72/936—
    • H10W72/9415—
    • H10W72/9445—
    • H10W72/952—
    • H10W74/15—
    • H10W90/724—

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
JP2015520404A 2012-06-25 2013-06-25 オフセットビア（ｖｉａｓ）を有する集積回路パッケージ Active JP5964511B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/532,126 US8624404B1 (en) 2012-06-25 2012-06-25 Integrated circuit package having offset vias
US13/532,126 2012-06-25
PCT/US2013/047634 WO2014004520A1 (en) 2012-06-25 2013-06-25 Integrated circuit package having offset vias

Publications (2)

Publication Number Publication Date
JP2015525968A JP2015525968A (ja) 2015-09-07
JP5964511B2 true JP5964511B2 (ja) 2016-08-03

Family

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Family Applications (1)

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JP2015520404A Active JP5964511B2 (ja) 2012-06-25 2013-06-25 オフセットビア（ｖｉａｓ）を有する集積回路パッケージ

Country Status (7)

Country Link
US (1) US8624404B1 (enExample)
EP (1) EP2865006A4 (enExample)
JP (1) JP5964511B2 (enExample)
KR (1) KR101569162B1 (enExample)
CN (2) CN110060977A (enExample)
IN (1) IN2014DN10923A (enExample)
WO (1) WO2014004520A1 (enExample)

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US10497657B1 (en) * 2018-06-13 2019-12-03 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
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US20230029763A1 (en) * 2021-07-30 2023-02-02 Cree, Inc. Interconnect metal openings through dielectric films
CN117059583B (zh) * 2023-10-12 2024-01-09 江苏芯德半导体科技有限公司 一种具有异质胶材的晶圆级扇出型封装结构及其封装方法
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Also Published As

Publication number Publication date
CN104956479A (zh) 2015-09-30
IN2014DN10923A (enExample) 2015-09-18
CN110060977A (zh) 2019-07-26
US8624404B1 (en) 2014-01-07
EP2865006A1 (en) 2015-04-29
JP2015525968A (ja) 2015-09-07
KR101569162B1 (ko) 2015-11-13
US20130341802A1 (en) 2013-12-26
EP2865006A4 (en) 2016-03-23
KR20150016641A (ko) 2015-02-12
WO2014004520A1 (en) 2014-01-03

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