IN2014DN10923A - - Google Patents

Info

Publication number
IN2014DN10923A
IN2014DN10923A IN10923DEN2014A IN2014DN10923A IN 2014DN10923 A IN2014DN10923 A IN 2014DN10923A IN 10923DEN2014 A IN10923DEN2014 A IN 10923DEN2014A IN 2014DN10923 A IN2014DN10923 A IN 2014DN10923A
Authority
IN
India
Prior art keywords
semiconductor chip
pad
substrate
extends
integrated circuit
Prior art date
Application number
Other languages
English (en)
Inventor
Michael Zhuoying Su
Fu Lei
Frank Kuechenmeister
Original Assignee
Advanced Micro Devices Inc
Michael Zhuoying Su
Frank Kuechenmeister
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc, Michael Zhuoying Su, Frank Kuechenmeister filed Critical Advanced Micro Devices Inc
Publication of IN2014DN10923A publication Critical patent/IN2014DN10923A/en

Links

Classifications

    • H10W74/147—
    • H10W72/012—
    • H10W72/019—
    • H10W72/20—
    • H10W72/90—
    • H10W20/082—
    • H10W42/121—
    • H10W72/01235—
    • H10W72/01255—
    • H10W72/01935—
    • H10W72/0198—
    • H10W72/072—
    • H10W72/07236—
    • H10W72/227—
    • H10W72/234—
    • H10W72/237—
    • H10W72/241—
    • H10W72/242—
    • H10W72/244—
    • H10W72/247—
    • H10W72/248—
    • H10W72/252—
    • H10W72/29—
    • H10W72/926—
    • H10W72/934—
    • H10W72/936—
    • H10W72/9415—
    • H10W72/9445—
    • H10W72/952—
    • H10W74/15—
    • H10W90/724—

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
IN10923DEN2014 2012-06-25 2013-06-25 IN2014DN10923A (enExample)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/532,126 US8624404B1 (en) 2012-06-25 2012-06-25 Integrated circuit package having offset vias
PCT/US2013/047634 WO2014004520A1 (en) 2012-06-25 2013-06-25 Integrated circuit package having offset vias

Publications (1)

Publication Number Publication Date
IN2014DN10923A true IN2014DN10923A (enExample) 2015-09-18

Family

ID=49773740

Family Applications (1)

Application Number Title Priority Date Filing Date
IN10923DEN2014 IN2014DN10923A (enExample) 2012-06-25 2013-06-25

Country Status (7)

Country Link
US (1) US8624404B1 (enExample)
EP (1) EP2865006A4 (enExample)
JP (1) JP5964511B2 (enExample)
KR (1) KR101569162B1 (enExample)
CN (2) CN110060977A (enExample)
IN (1) IN2014DN10923A (enExample)
WO (1) WO2014004520A1 (enExample)

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US10096639B2 (en) * 2016-10-10 2018-10-09 Sensors Unlimited, Inc. Bump structures for interconnecting focal plane arrays
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US10497657B1 (en) * 2018-06-13 2019-12-03 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
CN109004080B (zh) * 2018-08-10 2024-08-06 浙江熔城半导体有限公司 带有延伸双围堰及焊锡的芯片封装结构及其制作方法
KR102822948B1 (ko) * 2020-08-12 2025-06-20 삼성전자주식회사 배선 구조물 및 이를 포함하는 반도체 칩
US20230029763A1 (en) * 2021-07-30 2023-02-02 Cree, Inc. Interconnect metal openings through dielectric films
CN117059583B (zh) * 2023-10-12 2024-01-09 江苏芯德半导体科技有限公司 一种具有异质胶材的晶圆级扇出型封装结构及其封装方法
US12489073B1 (en) 2024-11-15 2025-12-02 Globalfoundries U.S. Inc. Acentric non-round electrical interconnections

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Also Published As

Publication number Publication date
JP5964511B2 (ja) 2016-08-03
CN104956479A (zh) 2015-09-30
CN110060977A (zh) 2019-07-26
US8624404B1 (en) 2014-01-07
EP2865006A1 (en) 2015-04-29
JP2015525968A (ja) 2015-09-07
KR101569162B1 (ko) 2015-11-13
US20130341802A1 (en) 2013-12-26
EP2865006A4 (en) 2016-03-23
KR20150016641A (ko) 2015-02-12
WO2014004520A1 (en) 2014-01-03

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