KR101569162B1 - 집적 회로 패키지, 집적 회로 다이 및 집적 회로 다이를 제조하는 방법 - Google Patents

집적 회로 패키지, 집적 회로 다이 및 집적 회로 다이를 제조하는 방법 Download PDF

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KR101569162B1
KR101569162B1 KR1020157001855A KR20157001855A KR101569162B1 KR 101569162 B1 KR101569162 B1 KR 101569162B1 KR 1020157001855 A KR1020157001855 A KR 1020157001855A KR 20157001855 A KR20157001855 A KR 20157001855A KR 101569162 B1 KR101569162 B1 KR 101569162B1
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integrated circuit
vias
semiconductor chip
center
insulating layer
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KR20150016641A (ko
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마이클 쥬오잉 수
푸 레이
프랭크 쿠에첸메이스터
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/14104—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
KR1020157001855A 2012-06-25 2013-06-25 집적 회로 패키지, 집적 회로 다이 및 집적 회로 다이를 제조하는 방법 Active KR101569162B1 (ko)

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US13/532,126 2012-06-25
US13/532,126 US8624404B1 (en) 2012-06-25 2012-06-25 Integrated circuit package having offset vias
PCT/US2013/047634 WO2014004520A1 (en) 2012-06-25 2013-06-25 Integrated circuit package having offset vias

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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6180801B2 (ja) * 2013-06-07 2017-08-16 ルネサスエレクトロニクス株式会社 半導体装置
JP6221499B2 (ja) * 2013-08-19 2017-11-01 富士通株式会社 電子装置及び電子装置の製造方法
US10096639B2 (en) 2016-10-10 2018-10-09 Sensors Unlimited, Inc. Bump structures for interconnecting focal plane arrays
DE102017128568A1 (de) * 2017-12-01 2019-06-06 Infineon Technologies Ag Halbleiterchip mit einer vielzahl von externen kontakten, chip-anordnung und verfahren zum überprüfen einer ausrichtung einer position eines halbleiterchips
US10497657B1 (en) * 2018-06-13 2019-12-03 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
CN109004080B (zh) * 2018-08-10 2024-08-06 浙江熔城半导体有限公司 带有延伸双围堰及焊锡的芯片封装结构及其制作方法
KR102822948B1 (ko) * 2020-08-12 2025-06-20 삼성전자주식회사 배선 구조물 및 이를 포함하는 반도체 칩
US20230029763A1 (en) * 2021-07-30 2023-02-02 Cree, Inc. Interconnect metal openings through dielectric films
CN117059583B (zh) * 2023-10-12 2024-01-09 江苏芯德半导体科技有限公司 一种具有异质胶材的晶圆级扇出型封装结构及其封装方法
US12489073B1 (en) 2024-11-15 2025-12-02 Globalfoundries U.S. Inc. Acentric non-round electrical interconnections

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070228561A1 (en) 2006-03-31 2007-10-04 Fujitsu Limited Semiconductor device and manufacturing method thereof
US7420131B2 (en) 2003-02-28 2008-09-02 Ngk Spark Plug Co., Ltd. Wiring substrate
US7529449B2 (en) 2005-03-14 2009-05-05 Fuji Xerox Co., Ltd. Substrate, device and method for forming a guidance structure in the substrate, and positioning method
US7834449B2 (en) 2007-04-30 2010-11-16 Broadcom Corporation Highly reliable low cost structure for wafer-level ball grid array packaging

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63305530A (ja) * 1987-06-05 1988-12-13 Hitachi Ltd 半導体装置の製造方法
KR950001962A (ko) * 1993-06-30 1995-01-04 김광호 반도체 칩 범프
JP3217624B2 (ja) * 1994-11-12 2001-10-09 東芝マイクロエレクトロニクス株式会社 半導体装置
US6107109A (en) * 1997-12-18 2000-08-22 Micron Technology, Inc. Method for fabricating a semiconductor interconnect with laser machined electrical paths through substrate
US6075290A (en) * 1998-02-26 2000-06-13 National Semiconductor Corporation Surface mount die: wafer level chip-scale package and process for making the same
JPH11340355A (ja) * 1998-05-25 1999-12-10 Nec Corp 半導体装置
JP3351355B2 (ja) * 1998-09-29 2002-11-25 株式会社デンソー 電子部品の実装構造
KR100411679B1 (ko) * 1999-03-16 2003-12-18 세이코 엡슨 가부시키가이샤 반도체 장치 및 그 제조 방법, 회로 기판 및 전자기기
US6545192B2 (en) 1999-05-11 2003-04-08 Shell Oil Company Process for separating olefins from saturated hydrocarbons
US7034402B1 (en) * 2000-06-28 2006-04-25 Intel Corporation Device with segmented ball limiting metallurgy
US6703069B1 (en) * 2002-09-30 2004-03-09 Intel Corporation Under bump metallurgy for lead-tin bump over copper pad
JP2005012065A (ja) * 2003-06-20 2005-01-13 Renesas Technology Corp 半導体装置およびその製造方法
TWI220308B (en) * 2003-08-07 2004-08-11 Advanced Semiconductor Eng Under bump metallurgic layer
US7197727B1 (en) 2003-11-04 2007-03-27 Advanced Micro Devices, Inc. Interconnect speed sensing circuitry
US7095116B1 (en) * 2003-12-01 2006-08-22 National Semiconductor Corporation Aluminum-free under bump metallization structure
US7259458B2 (en) 2004-08-18 2007-08-21 Advanced Micro Devices, Inc. Integrated circuit with increased heat transfer
JP4628731B2 (ja) * 2004-09-24 2011-02-09 株式会社フジクラ 電子部品及び電子装置
US20060227237A1 (en) 2005-03-31 2006-10-12 International Business Machines Corporation Video surveillance system and method with combined video and audio recognition
US7206703B1 (en) 2005-05-02 2007-04-17 Advanced Micro Devices, Inc. System and method for testing packaged devices using time domain reflectometry
TWI258176B (en) * 2005-05-12 2006-07-11 Siliconware Precision Industries Co Ltd Semiconductor device and fabrication method thereof
CN100382291C (zh) * 2005-05-17 2008-04-16 矽品精密工业股份有限公司 半导体装置及其制法
US20080124840A1 (en) 2006-07-31 2008-05-29 Su Michael Z Electrical Insulating Layer for Metallic Thermal Interface Material
US7616021B2 (en) 2007-01-18 2009-11-10 Advanced Micro Devices, Inc. Method and device for determining an operational lifetime of an integrated circuit device
US20080191318A1 (en) 2007-02-09 2008-08-14 Advanced Micro Devices, Inc. Semiconductor device and method of sawing semiconductor device
US8344505B2 (en) 2007-08-29 2013-01-01 Ati Technologies Ulc Wafer level packaging of semiconductor chips
US7679200B2 (en) 2007-09-11 2010-03-16 Globalfoundries Inc. Semiconductor chip with crack stop
US7812438B2 (en) * 2008-01-07 2010-10-12 International Business Machines Corporation Via offsetting to reduce stress under the first level interconnect (FLI) in microelectronics packaging
US20090278263A1 (en) * 2008-05-09 2009-11-12 Texas Instruments Incorporated Reliability wcsp layouts
US7737563B2 (en) 2008-06-04 2010-06-15 Globalfoundries Inc. Semiconductor chip with reinforcement structure
US8212357B2 (en) * 2008-08-08 2012-07-03 International Business Machines Corporation Combination via and pad structure for improved solder bump electromigration characteristics
US8293581B2 (en) 2009-02-18 2012-10-23 Globalfoundries Inc. Semiconductor chip with protective scribe structure
US7897433B2 (en) 2009-02-18 2011-03-01 Advanced Micro Devices, Inc. Semiconductor chip with reinforcement layer and method of making the same
US8072071B2 (en) * 2009-02-19 2011-12-06 Infineon Technologies Ag Semiconductor device including conductive element
US8198133B2 (en) * 2009-07-13 2012-06-12 International Business Machines Corporation Structures and methods to improve lead-free C4 interconnect reliability
US7977160B2 (en) 2009-08-10 2011-07-12 GlobalFoundries, Inc. Semiconductor devices having stress relief layers and methods for fabricating the same
US8269348B2 (en) * 2010-02-22 2012-09-18 Texas Instruments Incorporated IC die including RDL capture pads with notch having bonding connectors or its UBM pad over the notch
TWI478303B (zh) * 2010-09-27 2015-03-21 日月光半導體製造股份有限公司 具有金屬柱之晶片及具有金屬柱之晶片之封裝結構

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7420131B2 (en) 2003-02-28 2008-09-02 Ngk Spark Plug Co., Ltd. Wiring substrate
US7529449B2 (en) 2005-03-14 2009-05-05 Fuji Xerox Co., Ltd. Substrate, device and method for forming a guidance structure in the substrate, and positioning method
US20070228561A1 (en) 2006-03-31 2007-10-04 Fujitsu Limited Semiconductor device and manufacturing method thereof
US7834449B2 (en) 2007-04-30 2010-11-16 Broadcom Corporation Highly reliable low cost structure for wafer-level ball grid array packaging

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EP2865006A4 (en) 2016-03-23
EP2865006A1 (en) 2015-04-29
US8624404B1 (en) 2014-01-07
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