JP5878837B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP5878837B2
JP5878837B2 JP2012152502A JP2012152502A JP5878837B2 JP 5878837 B2 JP5878837 B2 JP 5878837B2 JP 2012152502 A JP2012152502 A JP 2012152502A JP 2012152502 A JP2012152502 A JP 2012152502A JP 5878837 B2 JP5878837 B2 JP 5878837B2
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JP
Japan
Prior art keywords
negative bias
port
bit line
bias reference
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2012152502A
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English (en)
Japanese (ja)
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JP2014017029A5 (enExample
JP2014017029A (ja
Inventor
英弘 藤原
英弘 藤原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2012152502A priority Critical patent/JP5878837B2/ja
Priority to US13/935,815 priority patent/US9171595B2/en
Publication of JP2014017029A publication Critical patent/JP2014017029A/ja
Publication of JP2014017029A5 publication Critical patent/JP2014017029A5/ja
Priority to US14/877,091 priority patent/US20160027502A1/en
Application granted granted Critical
Publication of JP5878837B2 publication Critical patent/JP5878837B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
JP2012152502A 2012-07-06 2012-07-06 半導体装置 Active JP5878837B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2012152502A JP5878837B2 (ja) 2012-07-06 2012-07-06 半導体装置
US13/935,815 US9171595B2 (en) 2012-07-06 2013-07-05 Semiconductor device including negative bias voltage generation circuit
US14/877,091 US20160027502A1 (en) 2012-07-06 2015-10-07 Semiconductor device including negative bias voltage generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012152502A JP5878837B2 (ja) 2012-07-06 2012-07-06 半導体装置

Publications (3)

Publication Number Publication Date
JP2014017029A JP2014017029A (ja) 2014-01-30
JP2014017029A5 JP2014017029A5 (enExample) 2015-04-02
JP5878837B2 true JP5878837B2 (ja) 2016-03-08

Family

ID=49878422

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012152502A Active JP5878837B2 (ja) 2012-07-06 2012-07-06 半導体装置

Country Status (2)

Country Link
US (2) US9171595B2 (enExample)
JP (1) JP5878837B2 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5777991B2 (ja) * 2011-09-22 2015-09-16 ルネサスエレクトロニクス株式会社 半導体装置
WO2015061370A1 (en) 2013-10-21 2015-04-30 Milwaukee Electric Tool Corporation Adapter for power tool devices
US10650882B2 (en) 2014-10-15 2020-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Static random access memory with a supplementary driver circuit and method of controlling the same
US10236055B1 (en) * 2014-12-12 2019-03-19 Altera Corporation Memory element write-assist circuitry with dummy bit lines
US10032509B2 (en) * 2015-03-30 2018-07-24 Toshiba Memory Corporation Semiconductor memory device including variable resistance element
US10892008B2 (en) 2018-06-15 2021-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Multi word line assertion
DE102019115978B4 (de) 2018-06-15 2022-03-31 Taiwan Semiconductor Manufacturing Co., Ltd. Aktivierung mehrerer wortleitungen
WO2020234630A1 (fr) * 2019-05-22 2020-11-26 Garmin Switzerland Procede d'optimisation de la conduction electrique a travers une interface metal/oxyde natif/metal
JP7234172B2 (ja) 2020-03-05 2023-03-07 株式会社東芝 半導体記憶装置
TWI809384B (zh) * 2020-04-28 2023-07-21 台灣積體電路製造股份有限公司 積體電路結構及其形成方法
US12414311B2 (en) 2020-04-28 2025-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit with feol resistor
JPWO2024029067A1 (enExample) * 2022-08-05 2024-02-08
JP2024070974A (ja) * 2022-11-14 2024-05-24 ローム株式会社 半導体装置
CN220381786U (zh) * 2023-07-07 2024-01-23 台湾积体电路制造股份有限公司 记忆体装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4936749B2 (ja) * 2006-03-13 2012-05-23 株式会社東芝 半導体記憶装置
US20070247885A1 (en) * 2006-04-25 2007-10-25 Renesas Technology Corp. Content addressable memory
US7379354B2 (en) * 2006-05-16 2008-05-27 Texas Instruments Incorporated Methods and apparatus to provide voltage control for SRAM write assist circuits
JP5256512B2 (ja) * 2008-06-06 2013-08-07 ルネサスエレクトロニクス株式会社 半導体記憶装置
JP4802257B2 (ja) * 2009-03-16 2011-10-26 株式会社東芝 半導体記憶装置
JP5264611B2 (ja) * 2009-04-28 2013-08-14 パナソニック株式会社 半導体記憶装置
US8300489B2 (en) * 2010-01-12 2012-10-30 International Business Machines Corporation Charge pump system and method utilizing adjustable output charge and compilation system and method for use by the charge pump
JP2012069214A (ja) * 2010-09-24 2012-04-05 Toshiba Corp ビット線負電位回路および半導体記憶装置
JP5777991B2 (ja) * 2011-09-22 2015-09-16 ルネサスエレクトロニクス株式会社 半導体装置

Also Published As

Publication number Publication date
US9171595B2 (en) 2015-10-27
US20140010027A1 (en) 2014-01-09
US20160027502A1 (en) 2016-01-28
JP2014017029A (ja) 2014-01-30

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