JP5789398B2 - 半導体装置の作製方法 - Google Patents
半導体装置の作製方法 Download PDFInfo
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- JP5789398B2 JP5789398B2 JP2011084321A JP2011084321A JP5789398B2 JP 5789398 B2 JP5789398 B2 JP 5789398B2 JP 2011084321 A JP2011084321 A JP 2011084321A JP 2011084321 A JP2011084321 A JP 2011084321A JP 5789398 B2 JP5789398 B2 JP 5789398B2
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- insulating film
- transistor
- film
- oxide semiconductor
- electrode
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- 238000000859 sublimation Methods 0.000 description 1
- 230000008022 sublimation Effects 0.000 description 1
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
- PPMWWXLUCOODDK-UHFFFAOYSA-N tetrafluorogermane Chemical compound F[Ge](F)(F)F PPMWWXLUCOODDK-UHFFFAOYSA-N 0.000 description 1
- 150000003608 titanium Chemical class 0.000 description 1
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 1
- 239000005052 trichlorosilane Substances 0.000 description 1
- 229910001930 tungsten oxide Inorganic materials 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
- OYQCBJZGELKKPM-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O-2].[Zn+2].[O-2].[In+3] OYQCBJZGELKKPM-UHFFFAOYSA-N 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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Description
本実施の形態では、開示する発明の一態様に係る半導体装置の構成およびその作製方法について、図1及び図2を参照して説明する。
図1には、半導体装置の構成例を示す。
次に、上記半導体装置の作製方法の例について、図2を参照して説明する。ここで、図2は図1に示すトランジスタ162の作製方法の例について示す図である。
本実施の形態では、開示する発明の別の一態様に係る半導体装置の構成およびその作製方法について、図3乃至図5を参照して説明する。
図3は、半導体装置の構成の一例である。図3(A)には、半導体装置の断面を、図3(B)には、半導体装置の平面を、図3(C)には半導体装置の回路構成を、それぞれ示す。なお、当該半導体装置の動作の詳細については後の実施の形態において詳述するから、本実施の形態では主として半導体装置の構成について述べるものとする。なお、図3に示す半導体装置は、所定の機能を有する半導体装置の一例であって、開示する発明の半導体装置をもれなく表現したものではない。開示する発明に係る半導体装置は、電極の接続関係等を適宜変更して、その他の機能を有することが可能である。
次に、上記半導体装置の作製方法の一例について図4および図5を用いて説明する。なお、図4及び図5は図3(B)のA1−A2およびB1−B2における断面に相当する。なお、トランジスタ162の作製方法は先の実施の形態と同様であるため、ここでは主として、トランジスタ160の作製方法について説明する。
本実施の形態では、開示する発明の一態様に係る半導体装置の応用例について、図6を参照して説明する。ここでは、記憶装置の一例について説明する。なお、回路図においては、酸化物半導体を用いたトランジスタであることを示すために、OSの符号を併せて付す場合がある。
本実施の形態では、開示する発明の一態様に係る半導体装置の応用例について、図7および図8を用いて説明する。ここでは、記憶装置の一例について説明する。なお、回路図においては、酸化物半導体を用いたトランジスタであることを示すために、OSの符号を併せて付す場合がある。
本実施の形態では、開示する発明の一態様に係る半導体装置の応用例について、図9を参照して説明する。ここでは、中央演算処理装置(CPU)について説明する。
本実施の形態では、開示する発明の一態様に係る半導体装置の応用例について、図10を参照して説明する。ここでは、対象物の情報を読み取るイメージセンサ機能を有する半導体装置の一例について説明する。なお、回路図においては、酸化物半導体を用いたトランジスタであることを示すために、OSの符号を併せて付す場合がある。
本実施の形態では、上述の実施の形態で説明した半導体装置を電子機器に適用する場合について、図11を用いて説明する。本実施の形態では、コンピュータ、携帯電話機(携帯電話、携帯電話装置ともいう)、携帯情報端末(携帯型ゲーム機、音響再生装置なども含む)、デジタルカメラ、デジタルビデオカメラ、電子ペーパー、テレビジョン装置(テレビ、またはテレビジョン受信機ともいう)などの電子機器に、上述の半導体装置を適用する場合について説明する。
1.In−Ga−Zn−O系の酸化物半導体(酸化物半導体層の材料)
バンドギャップEg:3.15eV、電子親和力χ:4.3eV、比誘電率:15、電子移動度:10cm2/Vs
2.窒化チタン(ソース電極およびドレイン電極の材料)
仕事関数φM:3.9eV
3.酸化ハフニウム(ゲート絶縁膜の材料)
比誘電率:15
4.タングステン(ゲート電極の材料)
仕事関数φM:4.9eV
1.In−Ga−Zn−O系の酸化物半導体(酸化物半導体層の材料)
バンドギャップEg:3.15eV、電子親和力χ:4.3eV、比誘電率:15、電子移動度:10cm2/Vs
2.窒化チタン(ソース電極およびドレイン電極の材料)
仕事関数φM:3.9eV
3.酸化ハフニウム(ゲート絶縁膜の材料)
比誘電率:15
4.タングステン(ゲート電極の材料)
仕事関数φM:4.9eV
102 保護層
104 半導体領域
106 素子分離絶縁膜
108 ゲート絶縁膜
110 ゲート電極
116 チャネル形成領域
120 不純物領域
122 金属層
124 金属化合物領域
130 絶縁膜
140 基体
141 マスク
141a マスク
141b マスク
142 導電膜
142a ソース電極
142b ドレイン電極
143 絶縁膜
143a 絶縁膜
144 酸化物半導体膜
146 ゲート絶縁膜
148a ゲート電極
148b 電極
150 絶縁膜
152 絶縁膜
160 トランジスタ
162 トランジスタ
164 容量素子
542a ソース電極
542b ドレイン電極
543a 絶縁膜
544 酸化物半導体層
546 ゲート絶縁膜
548a ゲート電極
562 トランジスタ
642a ソース電極
642b ドレイン電極
644 酸化物半導体層
646 ゲート絶縁膜
648a ゲート電極
662 トランジスタ
701 筐体
702 筐体
703 表示部
704 キーボード
711 本体
712 スタイラス
713 表示部
714 操作ボタン
715 外部インターフェイス
720 電子書籍
721 筐体
723 筐体
725 表示部
727 表示部
731 電源
733 操作キー
735 スピーカー
737 軸部
740 筐体
741 筐体
742 表示パネル
743 スピーカー
744 マイクロフォン
745 操作キー
746 ポインティングデバイス
747 カメラ用レンズ
748 外部接続端子
749 太陽電池セル
750 外部メモリスロット
761 本体
763 接眼部
764 操作スイッチ
765 表示部
766 バッテリー
767 表示部
770 テレビジョン装置
771 筐体
773 表示部
775 スタンド
780 リモコン操作機
1000 トランジスタ
1010 トランジスタ
1020 容量素子
1050 メモリセル
1101 CPU
1102 タイミングコントロール回路
1103 命令解析デコーダー
1104 レジスタアレイ
1105 アドレスロジックバッファ回路
1106 データバスインターフェイス
1107 ALU
1108 命令レジスタ
1202 フォトダイオード
1204 トランジスタ
1206 トランジスタ
1212 フォトダイオードリセット信号線
1214 ゲート信号線
1216 フォトセンサ出力信号線
1218 フォトセンサ基準信号線
1222 基板
1224 基板
1226a 半導体層
1226b 半導体層
1226c 半導体層
1228 接着層
1230 入射光
1234 絶縁膜
1236 層間絶縁膜
1238 層間絶縁膜
1240 ゲート電極層
1242 電極層
1244 電極層
Claims (6)
- 平坦な表面を有する基体上に第1の絶縁膜を形成し、
前記第1の絶縁膜上に第1のマスクを形成し、
前記第1のマスクにスリミング処理を行うことにより、第2のマスクを形成し、
前記第2のマスクを用いて前記第1の絶縁膜にエッチング処理を行うことにより、第2の絶縁膜を形成し、
前記基体および前記第2の絶縁膜を覆うように第1の導電膜を形成し、
前記第1の導電膜および前記第2の絶縁膜に研磨処理を行うことにより、略等しい厚さの第3の絶縁膜、ソース電極およびドレイン電極を形成し、
前記第3の絶縁膜、前記ソース電極および前記ドレイン電極上に酸化物半導体膜を形成し、
前記酸化物半導体膜上にゲート絶縁膜を形成し、
前記ゲート絶縁膜上の前記第3の絶縁膜と重畳する領域にゲート電極を形成し、
前記第3の絶縁膜上面の二乗平均平方根粗さ、前記ソース電極上面の二乗平均平方根粗さ、および前記ドレイン電極上面の二乗平均平方根粗さは、それぞれ1nm以下であり、
前記第3の絶縁膜上面の一部と前記ソース電極上面との高低差、または前記第3の絶縁膜上面の一部と前記ドレイン電極上面との高低差は、5nm未満である半導体装置の作製方法。 - チャネル形成領域と、前記チャネル形成領域上の第1のゲート絶縁膜と、前記チャネル形成領域と重畳する、前記第1のゲート絶縁膜上の第1のゲート電極と、前記チャネル形成領域と電気的に接続する第1のソース電極および第1のドレイン電極と、を有する第1のトランジスタを形成し、
前記第1のトランジスタを覆う平坦な表面を有する層間絶縁膜を形成し、
前記層間絶縁膜上に、第1の絶縁膜を形成し、
前記第1の絶縁膜上に第1のマスクを形成し、
前記第1のマスクにスリミング処理を行うことにより、第2のマスクを形成し、
前記第2のマスクを用いて前記第1の絶縁膜にエッチング処理を行うことにより、前記層間絶絶縁膜上に第2の絶縁膜を形成し、
前記層間絶縁膜および前記第2の絶縁膜を覆うように第1の導電膜を形成し、
前記第1の導電膜および前記第2の絶縁膜に研磨処理を行うことにより、略等しい厚さの第3の絶縁膜、第2のソース電極および第2のドレイン電極を形成し、
前記第3の絶縁膜、前記第2のソース電極および前記第2のドレイン電極上に酸化物半導体膜を形成し、
前記酸化物半導体膜上に、第2のゲート絶縁膜を形成し、
前記第2のゲート絶縁膜上の前記第3の絶縁膜と重畳する領域に第2のゲート電極を形成し、
前記第3の絶縁膜上面の二乗平均平方根粗さ、前記第2のソース電極上面の二乗平均平方根粗さ、および前記第2のドレイン電極上面の二乗平均平方根粗さは、それぞれ1nm以下であり、
前記第3の絶縁膜上面の一部と前記第2のソース電極上面との高低差、または前記第3の絶縁膜上面の一部と前記第2のドレイン電極上面との高低差は、5nm未満である半導体装置の作製方法。 - 請求項1又は2において、
前記平坦な表面は、二乗平均平方根粗さが1nm以下の表面とする半導体装置の作製方法。 - 請求項1乃至3のいずれか一において、
前記スリミング処理は、酸素ラジカルを用いたアッシング処理により行う半導体装置の作製方法。 - 請求項1乃至4のいずれか一において、
前記研磨処理は、化学的機械研磨により行う半導体装置の作製方法。 - 請求項1乃至5のいずれか一において、
前記第1の絶縁膜は、スパッタ処理を用いて形成する半導体装置の作製方法。
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KR102233959B1 (ko) * | 2011-01-28 | 2021-03-29 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치의 제작 방법 및 반도체 장치 |
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WO2011125806A1 (en) | 2011-10-13 |
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US20110250724A1 (en) | 2011-10-13 |
US8431449B2 (en) | 2013-04-30 |
JP2011233877A (ja) | 2011-11-17 |
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