JP5773306B2 - 半導体素子構造を形成する方法および装置 - Google Patents

半導体素子構造を形成する方法および装置 Download PDF

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JP5773306B2
JP5773306B2 JP2011004797A JP2011004797A JP5773306B2 JP 5773306 B2 JP5773306 B2 JP 5773306B2 JP 2011004797 A JP2011004797 A JP 2011004797A JP 2011004797 A JP2011004797 A JP 2011004797A JP 5773306 B2 JP5773306 B2 JP 5773306B2
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layer
dielectric
copper
substrate
metal
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JP2011146711A5 (enExample
JP2011146711A (ja
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バナージ、アナンダ
アンドリュー アントネリ、ジョージ
アンドリュー アントネリ、ジョージ
ローリン、ジェニファー オ
ローリン、ジェニファー オ
スリラム、マンディヤム
シュラヴェンディジク、バート ヴァン
シュラヴェンディジク、バート ヴァン
ヴァラダラジャン、セシャサイー
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Novellus Systems Inc
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Novellus Systems Inc
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Priority claimed from US12/688,154 external-priority patent/US8268722B2/en
Priority claimed from US12/689,803 external-priority patent/US7858510B1/en
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Publication of JP2011146711A publication Critical patent/JP2011146711A/ja
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02043Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02046Dry cleaning only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02312Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
    • H01L21/02315Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
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    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2011004797A 2010-01-15 2011-01-13 半導体素子構造を形成する方法および装置 Active JP5773306B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US12/688,154 2010-01-15
US12/688,154 US8268722B2 (en) 2009-06-03 2010-01-15 Interfacial capping layers for interconnects
US12/689,803 2010-01-19
US12/689,803 US7858510B1 (en) 2008-02-28 2010-01-19 Interfacial layers for electromigration resistance improvement in damascene interconnects

Publications (3)

Publication Number Publication Date
JP2011146711A JP2011146711A (ja) 2011-07-28
JP2011146711A5 JP2011146711A5 (enExample) 2014-02-27
JP5773306B2 true JP5773306B2 (ja) 2015-09-02

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JP2011004797A Active JP5773306B2 (ja) 2010-01-15 2011-01-13 半導体素子構造を形成する方法および装置

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JP (1) JP5773306B2 (enExample)
KR (1) KR101742825B1 (enExample)
CN (1) CN102130046B (enExample)
TW (2) TWI612618B (enExample)

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US7727881B1 (en) 2004-11-03 2010-06-01 Novellus Systems, Inc. Protective self-aligned buffer layers for damascene interconnects
US7727880B1 (en) 2004-11-03 2010-06-01 Novellus Systems, Inc. Protective self-aligned buffer layers for damascene interconnects
WO2012167141A2 (en) 2011-06-03 2012-12-06 Novellus Systems, Inc. Metal and silicon containing capping layers for interconnects
CN104008995B (zh) * 2013-02-22 2017-09-01 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法
EP2965347A4 (en) * 2013-03-05 2017-02-15 Entegris, Inc. Ion implantation compositions, systems, and methods
WO2015013266A1 (en) * 2013-07-24 2015-01-29 Applied Materials, Inc Cobalt substrate processing systems, apparatus, and methods
CN104576514B (zh) * 2013-10-29 2017-11-24 中芯国际集成电路制造(上海)有限公司 半导体器件的制备方法
CN104637864B (zh) * 2013-11-14 2017-11-24 中芯国际集成电路制造(上海)有限公司 提高数据保持能力的方法
US9368448B2 (en) * 2013-12-20 2016-06-14 Applied Materials, Inc. Metal-containing films as dielectric capping barrier for advanced interconnects
US9465071B2 (en) 2014-03-04 2016-10-11 Mediatek Inc. Method and apparatus for generating featured scan pattern
US10319908B2 (en) * 2014-05-01 2019-06-11 Crossbar, Inc. Integrative resistive memory in backend metal layers
US9633896B1 (en) 2015-10-09 2017-04-25 Lam Research Corporation Methods for formation of low-k aluminum-containing etch stop films
WO2018063815A1 (en) * 2016-10-02 2018-04-05 Applied Materials, Inc. Doped selective metal caps to improve copper electromigration with ruthenium liner
US9859153B1 (en) * 2016-11-14 2018-01-02 Lam Research Corporation Deposition of aluminum oxide etch stop layers
CN107256845A (zh) * 2017-05-25 2017-10-17 上海集成电路研发中心有限公司 一种铜互连结构及其制造方法
US20190127212A1 (en) * 2017-10-31 2019-05-02 Texas Instruments Incorporated Forming a passivation coating for mems devices
US10741440B2 (en) * 2018-06-05 2020-08-11 Lam Research Corporation Metal liner passivation and adhesion enhancement by zinc doping
US10707119B1 (en) * 2019-01-14 2020-07-07 Globalfoundries Inc. Interconnect structures with airgaps and dielectric-capped interconnects
CN111769074B (zh) * 2019-04-02 2024-09-27 长鑫存储技术有限公司 半导体互连结构及其制作方法
IL296563A (en) 2020-04-21 2022-11-01 Praxair Technology Inc Novel methods for gas phase selective etching of silicon-germanium layers
CN114429990A (zh) * 2020-10-29 2022-05-03 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US11581258B2 (en) * 2021-01-13 2023-02-14 Nanya Technology Corporation Semiconductor device structure with manganese-containing interconnect structure and method for forming the same
US11961735B2 (en) * 2021-06-04 2024-04-16 Tokyo Electron Limited Cyclic plasma processing

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US6605531B1 (en) * 1997-11-26 2003-08-12 Applied Materials, Inc. Hole-filling technique using CVD aluminum and PVD aluminum integration
US20020048926A1 (en) * 2000-09-14 2002-04-25 Konecni Anthony J. Method for forming a self-aligned copper capping diffusion barrier
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Also Published As

Publication number Publication date
TW201138024A (en) 2011-11-01
TWI612618B (zh) 2018-01-21
CN102130046A (zh) 2011-07-20
TW201709418A (zh) 2017-03-01
KR101742825B1 (ko) 2017-06-01
CN102130046B (zh) 2015-01-14
KR20110084130A (ko) 2011-07-21
JP2011146711A (ja) 2011-07-28

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