JP5773306B2 - 半導体素子構造を形成する方法および装置 - Google Patents
半導体素子構造を形成する方法および装置 Download PDFInfo
- Publication number
- JP5773306B2 JP5773306B2 JP2011004797A JP2011004797A JP5773306B2 JP 5773306 B2 JP5773306 B2 JP 5773306B2 JP 2011004797 A JP2011004797 A JP 2011004797A JP 2011004797 A JP2011004797 A JP 2011004797A JP 5773306 B2 JP5773306 B2 JP 5773306B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- dielectric
- copper
- substrate
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
- H01L21/02046—Dry cleaning only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
- H01L21/02315—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/688,154 | 2010-01-15 | ||
| US12/688,154 US8268722B2 (en) | 2009-06-03 | 2010-01-15 | Interfacial capping layers for interconnects |
| US12/689,803 | 2010-01-19 | ||
| US12/689,803 US7858510B1 (en) | 2008-02-28 | 2010-01-19 | Interfacial layers for electromigration resistance improvement in damascene interconnects |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2011146711A JP2011146711A (ja) | 2011-07-28 |
| JP2011146711A5 JP2011146711A5 (enExample) | 2014-02-27 |
| JP5773306B2 true JP5773306B2 (ja) | 2015-09-02 |
Family
ID=44268066
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2011004797A Active JP5773306B2 (ja) | 2010-01-15 | 2011-01-13 | 半導体素子構造を形成する方法および装置 |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP5773306B2 (enExample) |
| KR (1) | KR101742825B1 (enExample) |
| CN (1) | CN102130046B (enExample) |
| TW (2) | TWI612618B (enExample) |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7727881B1 (en) | 2004-11-03 | 2010-06-01 | Novellus Systems, Inc. | Protective self-aligned buffer layers for damascene interconnects |
| US7727880B1 (en) | 2004-11-03 | 2010-06-01 | Novellus Systems, Inc. | Protective self-aligned buffer layers for damascene interconnects |
| WO2012167141A2 (en) | 2011-06-03 | 2012-12-06 | Novellus Systems, Inc. | Metal and silicon containing capping layers for interconnects |
| CN104008995B (zh) * | 2013-02-22 | 2017-09-01 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制备方法 |
| EP2965347A4 (en) * | 2013-03-05 | 2017-02-15 | Entegris, Inc. | Ion implantation compositions, systems, and methods |
| WO2015013266A1 (en) * | 2013-07-24 | 2015-01-29 | Applied Materials, Inc | Cobalt substrate processing systems, apparatus, and methods |
| CN104576514B (zh) * | 2013-10-29 | 2017-11-24 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的制备方法 |
| CN104637864B (zh) * | 2013-11-14 | 2017-11-24 | 中芯国际集成电路制造(上海)有限公司 | 提高数据保持能力的方法 |
| US9368448B2 (en) * | 2013-12-20 | 2016-06-14 | Applied Materials, Inc. | Metal-containing films as dielectric capping barrier for advanced interconnects |
| US9465071B2 (en) | 2014-03-04 | 2016-10-11 | Mediatek Inc. | Method and apparatus for generating featured scan pattern |
| US10319908B2 (en) * | 2014-05-01 | 2019-06-11 | Crossbar, Inc. | Integrative resistive memory in backend metal layers |
| US9633896B1 (en) | 2015-10-09 | 2017-04-25 | Lam Research Corporation | Methods for formation of low-k aluminum-containing etch stop films |
| WO2018063815A1 (en) * | 2016-10-02 | 2018-04-05 | Applied Materials, Inc. | Doped selective metal caps to improve copper electromigration with ruthenium liner |
| US9859153B1 (en) * | 2016-11-14 | 2018-01-02 | Lam Research Corporation | Deposition of aluminum oxide etch stop layers |
| CN107256845A (zh) * | 2017-05-25 | 2017-10-17 | 上海集成电路研发中心有限公司 | 一种铜互连结构及其制造方法 |
| US20190127212A1 (en) * | 2017-10-31 | 2019-05-02 | Texas Instruments Incorporated | Forming a passivation coating for mems devices |
| US10741440B2 (en) * | 2018-06-05 | 2020-08-11 | Lam Research Corporation | Metal liner passivation and adhesion enhancement by zinc doping |
| US10707119B1 (en) * | 2019-01-14 | 2020-07-07 | Globalfoundries Inc. | Interconnect structures with airgaps and dielectric-capped interconnects |
| CN111769074B (zh) * | 2019-04-02 | 2024-09-27 | 长鑫存储技术有限公司 | 半导体互连结构及其制作方法 |
| IL296563A (en) | 2020-04-21 | 2022-11-01 | Praxair Technology Inc | Novel methods for gas phase selective etching of silicon-germanium layers |
| CN114429990A (zh) * | 2020-10-29 | 2022-05-03 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
| US11581258B2 (en) * | 2021-01-13 | 2023-02-14 | Nanya Technology Corporation | Semiconductor device structure with manganese-containing interconnect structure and method for forming the same |
| US11961735B2 (en) * | 2021-06-04 | 2024-04-16 | Tokyo Electron Limited | Cyclic plasma processing |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0765179B2 (ja) * | 1987-05-15 | 1995-07-12 | 日本電信電話株式会社 | 化学的気相成長方法 |
| US6605531B1 (en) * | 1997-11-26 | 2003-08-12 | Applied Materials, Inc. | Hole-filling technique using CVD aluminum and PVD aluminum integration |
| US20020048926A1 (en) * | 2000-09-14 | 2002-04-25 | Konecni Anthony J. | Method for forming a self-aligned copper capping diffusion barrier |
| US6664182B2 (en) * | 2001-04-25 | 2003-12-16 | Macronix International Co. Ltd. | Method of improving the interlayer adhesion property of low-k layers in a dual damascene process |
| US6518167B1 (en) * | 2002-04-16 | 2003-02-11 | Advanced Micro Devices, Inc. | Method of forming a metal or metal nitride interface layer between silicon nitride and copper |
| WO2004040642A1 (en) * | 2002-10-29 | 2004-05-13 | Asm America, Inc. | Oxygen bridge structures and methods |
| KR100564801B1 (ko) | 2003-12-30 | 2006-03-28 | 동부아남반도체 주식회사 | 반도체 제조 방법 |
| US7102232B2 (en) * | 2004-04-19 | 2006-09-05 | International Business Machines Corporation | Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer |
| US7704873B1 (en) * | 2004-11-03 | 2010-04-27 | Novellus Systems, Inc. | Protective self-aligned buffer layers for damascene interconnects |
| TW200802703A (en) * | 2005-11-28 | 2008-01-01 | Nxp Bv | Method of forming a self aligned copper capping layer |
| JP2007180408A (ja) * | 2005-12-28 | 2007-07-12 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
| DE102007004867B4 (de) * | 2007-01-31 | 2009-07-30 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Erhöhen der Zuverlässigkeit von kupferbasierten Metallisierungsstrukturen in einem Mikrostrukturbauelement durch Anwenden von Aluminiumnitrid |
| US7754588B2 (en) * | 2007-09-28 | 2010-07-13 | Tel Epion Inc. | Method to improve a copper/dielectric interface in semiconductor devices |
-
2011
- 2011-01-13 JP JP2011004797A patent/JP5773306B2/ja active Active
- 2011-01-14 TW TW100101507A patent/TWI612618B/zh active
- 2011-01-14 CN CN201110021170.4A patent/CN102130046B/zh active Active
- 2011-01-14 TW TW105123303A patent/TW201709418A/zh unknown
- 2011-01-17 KR KR1020110004334A patent/KR101742825B1/ko active Active
Also Published As
| Publication number | Publication date |
|---|---|
| TW201138024A (en) | 2011-11-01 |
| TWI612618B (zh) | 2018-01-21 |
| CN102130046A (zh) | 2011-07-20 |
| TW201709418A (zh) | 2017-03-01 |
| KR101742825B1 (ko) | 2017-06-01 |
| CN102130046B (zh) | 2015-01-14 |
| KR20110084130A (ko) | 2011-07-21 |
| JP2011146711A (ja) | 2011-07-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5773306B2 (ja) | 半導体素子構造を形成する方法および装置 | |
| US7858510B1 (en) | Interfacial layers for electromigration resistance improvement in damascene interconnects | |
| US7799671B1 (en) | Interfacial layers for electromigration resistance improvement in damascene interconnects | |
| US8268722B2 (en) | Interfacial capping layers for interconnects | |
| US11587829B2 (en) | Doping control of metal nitride films | |
| TWI541938B (zh) | 用於互連的含金屬及矽覆蓋層 | |
| US7838441B2 (en) | Deposition and densification process for titanium nitride barrier layers | |
| KR102036245B1 (ko) | 구리 배리어 적용들을 위한 도핑된 탄탈룸 질화물 | |
| US20110244680A1 (en) | Surface cleaning and selective deposition of metal-containing cap layers for semiconductor devices | |
| TW201330174A (zh) | 高溫鎢金屬化製程 | |
| WO2023033901A1 (en) | Method of forming a metal liner for interconnect structures | |
| CN116325120A (zh) | 低电阻及高可靠性金属化模块 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110506 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140110 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20140110 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20141022 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20141028 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150123 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20150602 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20150619 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 5773306 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |