JP5684230B2 - 電気的に絶縁された裏面を有するバンプ付き自己分離型ＧａＮトランジスタチップ - Google Patents

電気的に絶縁された裏面を有するバンプ付き自己分離型ＧａＮトランジスタチップ Download PDF

Info

Publication number
JP5684230B2
JP5684230B2 JP2012504764A JP2012504764A JP5684230B2 JP 5684230 B2 JP5684230 B2 JP 5684230B2 JP 2012504764 A JP2012504764 A JP 2012504764A JP 2012504764 A JP2012504764 A JP 2012504764A JP 5684230 B2 JP5684230 B2 JP 5684230B2
Authority
JP
Japan
Prior art keywords
silicon substrate
transistor
heat sink
electrical connection
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2012504764A
Other languages
English (en)
Other versions
JP2012523695A (ja
Inventor
リドウ，アレキサンダー
ビーチ，ロバート
ナカタ，アラナ
カオ，ジャンジュン
Original Assignee
エフィシエント パワー コンヴァーション コーポレーション
エフィシエント パワー コンヴァーション コーポレーション
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by エフィシエント パワー コンヴァーション コーポレーション, エフィシエント パワー コンヴァーション コーポレーション filed Critical エフィシエント パワー コンヴァーション コーポレーション
Publication of JP2012523695A publication Critical patent/JP2012523695A/ja
Application granted granted Critical
Publication of JP5684230B2 publication Critical patent/JP5684230B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3178—Coating or filling in grooves made in the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Materials Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Thin Film Transistor (AREA)

Description

本発明は、シリコン基板を用いた半導体デバイスに関する。
シリコンに形成されるデバイスは、長年プリント回路板上に直接実装されていた。問題は、デバイスの裏面がなお電気的に活性な状態である場合があることであり、このことが裏面上の腐食と温度の上昇を引き起こし得る。ヒートシンクが冷却のために用いられた場合、デバイスの裏面上で絶縁がしばしば必要とされ、デバイスサイズとコストの増加を招く。
図１は、プリント回路板１７上に搭載された公知のデバイス１の表面の例を示す。プリント回路板１７は、銅配線１５を有する。はんだバンプ１４は、不動態化ポリイミド１６により分離されているが、デバイスの活性領域１３をプリント回路板１７上の銅配線１５に電気的及び物理的に接続している。デバイス１は、側壁１２と裏面１１を有する。側壁１２及び裏面１１は、前面の回路に電気的に接続されている。
図２は、シリコン基板１０の裏面から熱を取り去るためにデバイス１に付着させられたヒートシンク１９を示す。ヒートシンク１０がデバイス１の裏面１１に付着されたときに、ヒートシンク１９が前面に電気的に接続されている裏面１１との接触を通じて電気的に活性になるのを防止するために、シリコン基板１０とヒートシンク１９との間に絶縁体１８が追加されなければならない。しかしながら、絶縁体１８の追加は、ヒートシンク１９のデバイス１から熱を取り去る能力を不都合なほどに妨げる。
従って、上述の問題に対する解決策が必要とされ、とりわけ、デバイス１からの熱の通過を妨げる絶縁体層を必要とすることなく表面実装型デバイスの裏面に直接接続され得るデバイスが必要とされる。
本発明は、シリコン基板が電気的に活性となることを防ぐためにシリコン基板とＡｌＧａＮバッファ層との間の窒化アルミニウム（ＡｌＮ）シード層の絶縁体を含むことにより、及びデバイスの側壁から活性領域を分離することにより、従来技術における上述の問題を解決する。
従来技術のデバイスの側面図を示す。 ヒートシンクが付着した図１の従来技術のデバイスの側面図を示す。 本発明によるデバイスの側面図を示す。 ヒートシンクが付着した本発明のデバイスの側面図を示す。
以下、図面を参照して、本発明を実施するための形態の説明を行う。
本発明は、シリコン基板とＡｌＧａＮバッファ層との間の窒化アルミニウム（ＡｌＮ）シード層を含むことにより、シリコン基板が電気的に活性になるのを防止し、そして側壁をデバイスの活性領域から電気的に絶縁することにより、絶縁層の必要性を取り除き、これによりヒートシンクへの熱の伝導を改善する。
図３は、本発明の好ましい実施形態、つまりプリント回路板１７上に表面実装されたエンハンスメント型ＧａＮトランジスタ２を示す。従来技術にあるように、はんだバンプは、不動態化ポリイミド（又はポリイミド不動態皮膜、polyimid passivation）１６により分離され、デバイスの活性領域１３をプリント回路板１７上の銅配線１５に接続する。活性領域１３への電気的接続は、カルビン接続として用いられるソース電極の１つとともに、少なくとも１つのゲート電極と、少なくとも１つのドレイン電極と、少なくとも２つのソース電極とを含む。
本発明のデバイス２は、以下のように構成される。低温の、殆ど非晶質の窒化アルミニウム（ＡｌＮ）層がシリコン基板１０上に体積される。次に、ＡｌＮ層２１の形成を完成させながら、それより高い温度のＡｌＮ層が成長する。第２のＡｌＮ層は、多くの結晶欠陥（crystal imperfections）を有する。次に、ＡｌＧａＮの層がＡｌＮシード層２１を覆って成長し、結晶は良好になる。次いで、ドープされていないＧａＮ層が、均一な良好な結晶構造を有して成長する。活性デバイス領域１３のＡｌＧａＮキャップは、２ＤＥＧ（二次元電子ガス）を形成するために必要であるのだが、２ＤＥＧ（二次元電子ガス）がデバイスの端に到達するのを防止するために周辺でエッチング除去される。ドープされていないＧａＮ層は、端まで延びるが、下部のＡｌＧａＮバッファ層及びＡｌＮ層２１のように、電気を通さず、それ故デバイスの端を不活性にしておく。シリコン基板１０は同様に、ＡｌＮシード層２１により、活性デバイス領域１３から電気的に絶縁される。この電気的分離の結果として、デバイス２の裏面１１及び側壁１２上の腐食と温度は低減される。
図４は、熱を消散させるためにデバイス２の裏面１１に付着したヒートシンク１９を示す。シリコン基板１０を電気的に分離するための絶縁ＡｌＮシード層２１及び電気的に分離された側壁を含むことにより、ヒートシンク１０を、図２に示されるような絶縁体層１８を必要とすることなく、デバイス２の裏面１１に直接接続することを可能にする。それ故、デバイス２は、図２で示されたデバイス１の問題を有しない。即ち、デバイスから熱を取り去る能力を妨げる厚い絶縁体１８は存在しない。加えて、デバイス２はデバイス１よりももっと湿気に対する耐久性がある。デバイス２の上面を覆って表面不動態化を行えば十分であり、窒化シリコン、二酸化シリコン、又は両者の組み合わせが好ましい。オーバーモールディング（全周封止）は必要とされず、それ故、チップスケールパッケージ内にＧａＮパワートランジスタを設けることができる。
本発明の能動デバイスをシリコン基板上に複数取り込むことにより、様々な回路が形成され得る。例えば、本発明のＧａＮトランジスタは、ハーフブリッジ又はフルブリッジ構成において、シリコン基板上に取り込まれ得る。本発明のＧａＮパワートランジスタは、同一のシリコン基板上のより小さな駆動トランジスタによってもまた駆動され得る。
上述の説明及び図面は、ここに詳説された特徴及び利点を達成する発明の特定の実施形態の例示としてのみ考慮されるべきである。発明に対する変形及び置換がなさてもよい。従って、ここに詳説された発明の実施形態は上述の説明及び図面により限定されるとはみなさないものとする。

Claims (11)

  1. シリコン基板と、
    該シリコン基板上に配置された絶縁材料と、
    該絶縁材料を覆うとともに活性領域を含む化合物半導体材料と、
    前記活性領域への電気的接続の手段及び第１の不動態化材料とを含む上面とを有し、
    前記不動態化材料は窒化シリコン、二酸化シリコン、又は両者の組み合わせであり、
    前記活性化領域の端部はエッチング除去され、前記絶縁材料とともに当該半導体デバイスの絶縁外側側壁を形成すべく前記端部に前記不動態化材料が充填された半導体デバイス。
  2. 前記化合物半導体材料が、ガリウム、窒素、及びアルミニウムの組み合わせからなる様々な層から形成されている請求項１に記載のデバイス。
  3. エンハンスメント型トランジスタである請求項１に記載のデバイス。
  4. エンハンスメント型ＧａＮトランジスタである請求項２に記載のデバイス。
  5. ポリイミドプラスチックからなる第２の不動態化材料を更に有する請求項１に記載のデバイス。
  6. 前記基板と前記ヒートシンクとの間に絶縁体の層を有しないシリコン基板の表面に直接搭載されたヒートシンクを更に有する請求項１に記載のデバイス。
  7. 前記電気的接続は銅、鉛、銀、アンチモン、及び錫の様々な組み合わせからなるはんだバンプを含む請求項１に記載のデバイス。
  8. 前記電気的接続は、少なくとも１つのゲート電極、少なくとも１つのドレイン電極、及び少なくとも２つのソース電極とを含み、
    該ソース電極の１つはケルビン接続として用いられる請求項１に記載のデバイス。
  9. 複数の能動デバイスが、前記シリコン基板上に取り込まれた請求項３に記載のデバイス。
  10. 前記トランジスタは、ハーフブリッジ又はフルブリッジ構成である請求項３に記載のデバイス。
  11. 前記トランジスタは、同一の前記シリコン基板上の自分より小さい駆動トランジスタにより駆動される請求項３に記載のデバイス。
JP2012504764A 2009-04-08 2010-04-06 電気的に絶縁された裏面を有するバンプ付き自己分離型ＧａＮトランジスタチップ Active JP5684230B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16777309P 2009-04-08 2009-04-08
US61/167,773 2009-04-08
PCT/US2010/030049 WO2010117987A1 (en) 2009-04-08 2010-04-06 Bumped, self-isolated gan transistor chip with electrically isolated back surface

Publications (2)

Publication Number Publication Date
JP2012523695A JP2012523695A (ja) 2012-10-04
JP5684230B2 true JP5684230B2 (ja) 2015-03-11

Family

ID=42933676

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012504764A Active JP5684230B2 (ja) 2009-04-08 2010-04-06 電気的に絶縁された裏面を有するバンプ付き自己分離型ＧａＮトランジスタチップ

Country Status (7)

Country Link
US (1) US8785974B2 (ja)
JP (1) JP5684230B2 (ja)
KR (1) KR101660871B1 (ja)
CN (1) CN102439713B (ja)
DE (1) DE112010001560B4 (ja)
TW (1) TWI525765B (ja)
WO (1) WO2010117987A1 (ja)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101660871B1 (ko) * 2009-04-08 2016-09-28 이피션트 파워 컨버젼 코퍼레이션 전기적으로 격리된 후면을 구비한 범프 자기격리형 ＧａＮ 트랜지스터 칩
JP2014060358A (ja) 2012-09-19 2014-04-03 Toshiba Corp 半導体装置
WO2015026371A1 (en) 2013-08-23 2015-02-26 Intel Corporation High resistance layer for iii-v channel deposited on group iv substrates for mos transistors
CN103811365A (zh) * 2014-01-23 2014-05-21 南通富士通微电子股份有限公司 芯片级封装方法
US10685904B2 (en) * 2014-11-21 2020-06-16 Delta Electronics, Inc. Packaging device and manufacturing method thereof
US9324819B1 (en) 2014-11-26 2016-04-26 Delta Electronics, Inc. Semiconductor device
CN104780701A (zh) * 2015-04-17 2015-07-15 浪潮电子信息产业股份有限公司 一种简化pcb设计的散热装置
US10069002B2 (en) 2016-07-20 2018-09-04 Semiconductor Components Industries, Llc Bond-over-active circuity gallium nitride devices
WO2019021720A1 (ja) 2017-07-24 2019-01-31 株式会社村田製作所 半導体装置及び半導体装置の製造方法
KR102633137B1 (ko) 2018-01-23 2024-02-02 삼성전자주식회사 반도체 패키지
TWI683370B (zh) * 2019-03-12 2020-01-21 環球晶圓股份有限公司 半導體元件及其製造方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0513768A (ja) * 1991-07-08 1993-01-22 Fuji Electric Co Ltd 絶縁ゲート型バイポーラトランジスタ
JPH10256533A (ja) * 1997-03-17 1998-09-25 Toshiba Corp 化合物半導体装置およびその製造方法
CN1254443A (zh) * 1997-03-26 2000-05-24 株式会社日立制作所 扁平型半导体装置和使用该装置的电力变换装置
WO1998043301A1 (en) * 1997-03-26 1998-10-01 Hitachi, Ltd. Flat semiconductor device and power converter employing the same
US6683384B1 (en) * 1997-10-08 2004-01-27 Agere Systems Inc Air isolated crossovers
DE19935100B4 (de) * 1999-07-27 2004-10-28 Infineon Technologies Ag Halbbrückenkonfiguration
US6737301B2 (en) * 2000-07-13 2004-05-18 Isothermal Systems Research, Inc. Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor
JP2002110799A (ja) * 2000-09-27 2002-04-12 Toshiba Corp 半導体装置及びその製造方法
JP3520039B2 (ja) * 2000-10-05 2004-04-19 三洋電機株式会社 半導体装置および半導体モジュール
US6825559B2 (en) * 2003-01-02 2004-11-30 Cree, Inc. Group III nitride based flip-chip intergrated circuit and method for fabricating
DE10314842A1 (de) * 2003-04-01 2004-10-21 Siemens Ag Stromerfassungsschaltung für einen DC/DC-Wandler
JP3767585B2 (ja) * 2003-07-11 2006-04-19 株式会社デンソー 半導体装置
US7276423B2 (en) * 2003-12-05 2007-10-02 International Rectifier Corporation III-nitride device and method with variable epitaxial growth direction
US20050145851A1 (en) * 2003-12-17 2005-07-07 Nitronex Corporation Gallium nitride material structures including isolation regions and methods
US7071552B2 (en) * 2004-03-29 2006-07-04 Intel Corporation IC die with directly bonded liquid cooling device
JP4986406B2 (ja) * 2005-03-31 2012-07-25 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法
JP4946262B2 (ja) * 2006-08-18 2012-06-06 富士通セミコンダクター株式会社 半導体素子の実装方法及び半導体装置の製造方法
JP5186096B2 (ja) * 2006-10-12 2013-04-17 パナソニック株式会社 窒化物半導体トランジスタ及びその製造方法
JP2008117934A (ja) * 2006-11-02 2008-05-22 Nec Corp 半導体装置
CN101272096A (zh) * 2006-12-11 2008-09-24 国际整流器公司 单片集成的ⅲ族氮化物功率转换器
US7863877B2 (en) * 2006-12-11 2011-01-04 International Rectifier Corporation Monolithically integrated III-nitride power converter
US7745848B1 (en) * 2007-08-15 2010-06-29 Nitronex Corporation Gallium nitride material devices and thermal designs thereof
KR101660871B1 (ko) * 2009-04-08 2016-09-28 이피션트 파워 컨버젼 코퍼레이션 전기적으로 격리된 후면을 구비한 범프 자기격리형 ＧａＮ 트랜지스터 칩

Also Published As

Publication number Publication date
US20100258844A1 (en) 2010-10-14
KR20120004997A (ko) 2012-01-13
DE112010001560T5 (de) 2012-09-13
CN102439713B (zh) 2015-04-22
KR101660871B1 (ko) 2016-09-28
WO2010117987A1 (en) 2010-10-14
DE112010001560B4 (de) 2020-08-13
US8785974B2 (en) 2014-07-22
TWI525765B (zh) 2016-03-11
CN102439713A (zh) 2012-05-02
JP2012523695A (ja) 2012-10-04
TW201044530A (en) 2010-12-16

Similar Documents

Publication Publication Date Title
JP5684230B2 (ja) 電気的に絶縁された裏面を有するバンプ付き自己分離型ＧａＮトランジスタチップ
US7547964B2 (en) Device packages having a III-nitride based power semiconductor device
JP5433175B2 (ja) 半導体装置
US9520369B2 (en) Power module and method of packaging the same
US9536803B2 (en) Integrated power module with improved isolation and thermal conductivity
US10051742B2 (en) Power module and manufacturing method thereof
JP6979610B2 (ja) 半導体装置
JP2010283053A (ja) 半導体装置及びその製造方法
US20220384286A1 (en) Chip package structure with heat conductive layer
US8536701B2 (en) Electronic device packaging structure
US20200235067A1 (en) Electronic device flip chip package with exposed clip
US20110180855A1 (en) Non-direct bond copper isolated lateral wide band gap semiconductor device
US9881862B1 (en) Top side cooling for GaN power device
JP2011082523A (ja) 半導体デバイス用パッケージ
US11569211B2 (en) Semiconductor die with improved thermal insulation between a power portion and a peripheral portion, method of manufacturing, and package housing the die
US20240222204A1 (en) Semiconductor device
JP4460067B2 (ja) 半導体装置
TWM630809U (zh) 功率電晶體封裝元件
TW201935579A (zh) 半導體裝置及其製造方法
WO2006116249A2 (en) Device packages having a iii-nitride based power semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20130328

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20140526

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140603

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20140902

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20140909

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20141003

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20141224

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20150114

R150 Certificate of patent or registration of utility model

Ref document number: 5684230

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250