JP5684230B2 - 電気的に絶縁された裏面を有するバンプ付き自己分離型GaNトランジスタチップ - Google Patents

電気的に絶縁された裏面を有するバンプ付き自己分離型GaNトランジスタチップ Download PDF

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JP5684230B2
JP5684230B2 JP2012504764A JP2012504764A JP5684230B2 JP 5684230 B2 JP5684230 B2 JP 5684230B2 JP 2012504764 A JP2012504764 A JP 2012504764A JP 2012504764 A JP2012504764 A JP 2012504764A JP 5684230 B2 JP5684230 B2 JP 5684230B2
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silicon substrate
transistor
heat sink
electrical connection
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リドウ,アレキサンダー
ビーチ,ロバート
ナカタ,アラナ
カオ,ジャンジュン
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エフィシエント パワー コンヴァーション コーポレーション
エフィシエント パワー コンヴァーション コーポレーション
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Description

本発明は、シリコン基板を用いた半導体デバイスに関する。
シリコンに形成されるデバイスは、長年プリント回路板上に直接実装されていた。問題は、デバイスの裏面がなお電気的に活性な状態である場合があることであり、このことが裏面上の腐食と温度の上昇を引き起こし得る。ヒートシンクが冷却のために用いられた場合、デバイスの裏面上で絶縁がしばしば必要とされ、デバイスサイズとコストの増加を招く。
図1は、プリント回路板17上に搭載された公知のデバイス1の表面の例を示す。プリント回路板17は、銅配線15を有する。はんだバンプ14は、不動態化ポリイミド16により分離されているが、デバイスの活性領域13をプリント回路板17上の銅配線15に電気的及び物理的に接続している。デバイス1は、側壁12と裏面11を有する。側壁12及び裏面11は、前面の回路に電気的に接続されている。
図2は、シリコン基板10の裏面から熱を取り去るためにデバイス1に付着させられたヒートシンク19を示す。ヒートシンク10がデバイス1の裏面11に付着されたときに、ヒートシンク19が前面に電気的に接続されている裏面11との接触を通じて電気的に活性になるのを防止するために、シリコン基板10とヒートシンク19との間に絶縁体18が追加されなければならない。しかしながら、絶縁体18の追加は、ヒートシンク19のデバイス1から熱を取り去る能力を不都合なほどに妨げる。
従って、上述の問題に対する解決策が必要とされ、とりわけ、デバイス1からの熱の通過を妨げる絶縁体層を必要とすることなく表面実装型デバイスの裏面に直接接続され得るデバイスが必要とされる。
本発明は、シリコン基板が電気的に活性となることを防ぐためにシリコン基板とAlGaNバッファ層との間の窒化アルミニウム(AlN)シード層の絶縁体を含むことにより、及びデバイスの側壁から活性領域を分離することにより、従来技術における上述の問題を解決する。
従来技術のデバイスの側面図を示す。 ヒートシンクが付着した図1の従来技術のデバイスの側面図を示す。 本発明によるデバイスの側面図を示す。 ヒートシンクが付着した本発明のデバイスの側面図を示す。
以下、図面を参照して、本発明を実施するための形態の説明を行う。
本発明は、シリコン基板とAlGaNバッファ層との間の窒化アルミニウム(AlN)シード層を含むことにより、シリコン基板が電気的に活性になるのを防止し、そして側壁をデバイスの活性領域から電気的に絶縁することにより、絶縁層の必要性を取り除き、これによりヒートシンクへの熱の伝導を改善する。
図3は、本発明の好ましい実施形態、つまりプリント回路板17上に表面実装されたエンハンスメント型GaNトランジスタ2を示す。従来技術にあるように、はんだバンプは、不動態化ポリイミド(又はポリイミド不動態皮膜、polyimid passivation)16により分離され、デバイスの活性領域13をプリント回路板17上の銅配線15に接続する。活性領域13への電気的接続は、カルビン接続として用いられるソース電極の1つとともに、少なくとも1つのゲート電極と、少なくとも1つのドレイン電極と、少なくとも2つのソース電極とを含む。
本発明のデバイス2は、以下のように構成される。低温の、殆ど非晶質の窒化アルミニウム(AlN)層がシリコン基板10上に体積される。次に、AlN層21の形成を完成させながら、それより高い温度のAlN層が成長する。第2のAlN層は、多くの結晶欠陥(crystal imperfections)を有する。次に、AlGaNの層がAlNシード層21を覆って成長し、結晶は良好になる。次いで、ドープされていないGaN層が、均一な良好な結晶構造を有して成長する。活性デバイス領域13のAlGaNキャップは、2DEG(二次元電子ガス)を形成するために必要であるのだが、2DEG(二次元電子ガス)がデバイスの端に到達するのを防止するために周辺でエッチング除去される。ドープされていないGaN層は、端まで延びるが、下部のAlGaNバッファ層及びAlN層21のように、電気を通さず、それ故デバイスの端を不活性にしておく。シリコン基板10は同様に、AlNシード層21により、活性デバイス領域13から電気的に絶縁される。この電気的分離の結果として、デバイス2の裏面11及び側壁12上の腐食と温度は低減される。
図4は、熱を消散させるためにデバイス2の裏面11に付着したヒートシンク19を示す。シリコン基板10を電気的に分離するための絶縁AlNシード層21及び電気的に分離された側壁を含むことにより、ヒートシンク10を、図2に示されるような絶縁体層18を必要とすることなく、デバイス2の裏面11に直接接続することを可能にする。それ故、デバイス2は、図2で示されたデバイス1の問題を有しない。即ち、デバイスから熱を取り去る能力を妨げる厚い絶縁体18は存在しない。加えて、デバイス2はデバイス1よりももっと湿気に対する耐久性がある。デバイス2の上面を覆って表面不動態化を行えば十分であり、窒化シリコン、二酸化シリコン、又は両者の組み合わせが好ましい。オーバーモールディング(全周封止)は必要とされず、それ故、チップスケールパッケージ内にGaNパワートランジスタを設けることができる。
本発明の能動デバイスをシリコン基板上に複数取り込むことにより、様々な回路が形成され得る。例えば、本発明のGaNトランジスタは、ハーフブリッジ又はフルブリッジ構成において、シリコン基板上に取り込まれ得る。本発明のGaNパワートランジスタは、同一のシリコン基板上のより小さな駆動トランジスタによってもまた駆動され得る。
上述の説明及び図面は、ここに詳説された特徴及び利点を達成する発明の特定の実施形態の例示としてのみ考慮されるべきである。発明に対する変形及び置換がなさてもよい。従って、ここに詳説された発明の実施形態は上述の説明及び図面により限定されるとはみなさないものとする。

Claims (11)

  1. シリコン基板と、
    該シリコン基板上に配置された絶縁材料と、
    該絶縁材料を覆うとともに活性領域を含む化合物半導体材料と
    前記活性領域への電気的接続の手段及び第1の不動態化材料とを含む上面とを有し、
    前記不動態化材料は窒化シリコン、二酸化シリコン、又は両者の組み合わせであり、
    前記活性化領域の端部はエッチング除去され、前記絶縁材料とともに当該半導体デバイスの絶縁外側側壁を形成すべく前記端部に前記不動態化材料が充填された半導体デバイス。
  2. 前記化合物半導体材料が、ガリウム、窒素、及びアルミニウムの組み合わせからなる様々な層から形成されている請求項1に記載のデバイス。
  3. エンハンスメント型トランジスタである請求項1に記載のデバイス。
  4. エンハンスメント型GaNトランジスタである請求項2に記載のデバイス。
  5. ポリイミドプラスチックからなる第2の不動態化材料を更に有する請求項1に記載のデバイス。
  6. 前記基板と前記ヒートシンクとの間に絶縁体の層を有しないシリコン基板の表面に直接搭載されたヒートシンクを更に有する請求項1に記載のデバイス。
  7. 前記電気的接続は銅、鉛、銀、アンチモン、及び錫の様々な組み合わせからなるはんだバンプを含む請求項1に記載のデバイス。
  8. 前記電気的接続は、少なくとも1つのゲート電極、少なくとも1つのドレイン電極、及び少なくとも2つのソース電極とを含み、
    該ソース電極の1つはケルビン接続として用いられる請求項1に記載のデバイス。
  9. 複数の能動デバイスが、前記シリコン基板上に取り込まれた請求項3に記載のデバイス。
  10. 前記トランジスタは、ハーフブリッジ又はフルブリッジ構成である請求項3に記載のデバイス。
  11. 前記トランジスタは、同一の前記シリコン基板上の自分より小さい駆動トランジスタにより駆動される請求項3に記載のデバイス。
JP2012504764A 2009-04-08 2010-04-06 電気的に絶縁された裏面を有するバンプ付き自己分離型GaNトランジスタチップ Active JP5684230B2 (ja)

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