JP4946262B2 - 半導体素子の実装方法及び半導体装置の製造方法 - Google Patents
半導体素子の実装方法及び半導体装置の製造方法 Download PDFInfo
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- JP4946262B2 JP4946262B2 JP2006223280A JP2006223280A JP4946262B2 JP 4946262 B2 JP4946262 B2 JP 4946262B2 JP 2006223280 A JP2006223280 A JP 2006223280A JP 2006223280 A JP2006223280 A JP 2006223280A JP 4946262 B2 JP4946262 B2 JP 4946262B2
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- semiconductor element
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- H01L2924/11—Device type
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- H01L2924/1204—Optical Diode
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/1904—Component type
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- H01L2924/1904—Component type
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Description
本比較例にあっては、漸次冷却(徐冷)速度を、従来(約0.7℃/秒)よりも遅い約0.5℃/秒に設定して冷却を行う。
[第2の比較例]
本比較例にあっては、漸次冷却(徐冷)速度を、従来(約0.7℃/秒)よりも遅い約0.3℃/秒に設定して冷却を行う。
[第1の実施態様]
前記二つの比較例にあっては、リフロー加熱工程後の冷却工程において、冷却速度をより遅くすることにより、配線基板20から半導体素子10の多層配線層3中の強度が弱く脆弱な所謂Low−K材料から構成される層間絶縁膜5に応力が作用して層間剥離等が発生することを防止している。
[第2の実施態様]
前記第1の実施態様と同様に、リフロー加熱工程後の冷却工程中に、一定時間、所定の温度を保持し、その後再度温度を降下させる。冷却工程に於いて、これを少なくとも1回行い、50℃程に冷却する。
以上の説明に関し、更に以下の項を開示する。
(付記1) 半導体素子を、鉛(Pb)を含有しない外部接続用突起電極を介して配線基板に実装する方法であって、
前記半導体素子の外部接続用突起電極と前記配線基板とを接続するリフロー加熱処理を施した後に、
接続された前記半導体素子及び前記配線基板を、0.5℃/秒以下の冷却速度で冷却することを特徴とする半導体素子の実装方法。
(付記2) 付記1記載の半導体素子の実装方法であって、
前記冷却速度は、0.3℃/秒であることを特徴とする半導体素子の実装方法。
(付記3) 付記1又は2記載の半導体素子の実装方法であって、
前記外部接続用突起電極は、鉛を含有しない半田から構成されることを特徴とする半導体素子の実装方法。
(付記4) 付記1乃至3いずれか一項記載の半導体素子の実装方法であって、
前記配線基板は有機材料からなることを特徴とする半導体装置の実装方法。
(付記5) 付記4記載の半導体素子の実装方法であって、
前記半導体装置は、低誘電率材料から構成される層間絶縁膜を介して配線層が積層された多層配線構造を有することを特徴とする半導体装置の実装方法。
(付記6) 半導体素子を外部接続用突起電極を介して配線基板に実装する方法であって、
前記半導体素子の前記外部接続用突起電極と前記配線基板とを接続するためにリフロー加熱処理を施した後に、
接続された前記半導体素子及び前記配線基板を冷却して温度を降下させ、所定の温度に達すると、一定時間、当該所定の温度を保持し、前記一定時間経過後に、前記半導体素子及び前記配線基板を再度冷却して温度を降下させる、というステップ冷却が施されることを特徴とする半導体素子の実装方法。
(付記7) 付記6記載の半導体素子の実装方法であって、
前記ステップ冷却を1回以上施すことを特徴とする半導体素子の実装方法。
(付記8) 付記6又は7記載の半導体素子の実装方法であって、
前記所定の温度は80℃以上150℃以下の範囲の温度であることを特徴とする半導体素子の実装方法。
(付記9) 付記6乃至8いずれか一項記載の半導体素子の実装方法であって、
前記一定の時間は、120秒以上であることを特徴とする半導体素子の実装方法。
(付記10) 付記9記載の半導体素子の実装方法であって、
前記一定の時間は、約300秒以上であることを特徴とする半導体素子の実装方法。
(付記11) 付記6乃至10いずれか一項記載の半導体素子の実装方法であって、
前記外部接続用突起電極は、鉛を含有しない半田から構成されることを特徴とする半導体素子の実装方法。
(付記12) 付記6乃至11いずれか一項記載の半導体素子の実装方法であって、
前記配線基板は有機材料からなることを特徴とする半導体素子の実装方法。
(付記13) 付記12記載の半導体素子の実装方法であって、
前記半導体素子は、低誘電率材料から構成される層間絶縁膜を介して配線層が積層された多層配線構造を有することを特徴とする半導体素子の実装方法。
(付記14) 半導体素子の鉛(Pb)を含有しない外部接続用突起電極と配線基板とを接続するリフロー加熱処理を施した後に、
接続された前記半導体素子及び前記配線基板を、0.5℃/秒以下の冷却速度で冷却することを特徴とする半導体装置の製造方法。
(付記15) 半導体素子の外部接続用突起電極と配線基板とを接続するためにリフロー加熱処理を施した後に、接続された前記半導体素子及び前記配線基板を冷却して温度を降下させ、
所定の温度に達すると、一定時間、当該所定の温度を保持し、
前記一定時間経過後に、前記半導体素子及び前記配線基板を再度冷却して温度を降下させる、というステップ冷却が施されることを特徴とする半導体装置の製造方法。
4 配線層
5 層間絶縁膜
9 外部接続用突起電極
10 半導体素子
20 配線基板
Claims (3)
- 半導体素子を、鉛(Pb)を含有しない外部接続用突起電極を介して配線基板に実装する方法であって、
Low−K材料から構成される層間絶縁膜を有する前記半導体素子の電極パッドを覆うバンプ下地金属に配設された前記外部接続用突起電極と前記配線基板とを接続するためにリフロー加熱処理を施した後に、
接続された前記半導体素子及び前記配線基板を冷却して温度を降下させ、所定の温度に達すると、一定時間、当該所定の温度を保持し、前記一定時間経過後に、前記半導体素子及び前記配線基板を再度冷却して50℃まで温度を降下させる、というステップ冷却が施され、
前記所定の温度は80℃以上150℃以下の範囲の温度であり、
前記鉛(Pb)を含有しない外部接続用突起電極は、錫(Sn)−銀(Ag)、又は錫(Sn)−銀(Ag)−銅(Cu)からなる半田であり、前記半田の融点は217〜220℃であることを特徴とする半導体素子の実装方法。 - 請求項1記載の半導体素子の実装方法であって、
前記ステップ冷却を1回以上施すことを特徴とする半導体素子の実装方法。 - 請求項1又は2記載の半導体素子の実装方法であって、
前記一定の時間は、120秒以上であることを特徴とする半導体素子の実装方法。
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JP2006223280A JP4946262B2 (ja) | 2006-08-18 | 2006-08-18 | 半導体素子の実装方法及び半導体装置の製造方法 |
TW096101591A TWI331385B (en) | 2006-08-18 | 2007-01-16 | Mounting method of semiconductor element and manufacturing method of semiconductor device |
US11/653,954 US7879713B2 (en) | 2006-08-18 | 2007-01-17 | Mounting method of semiconductor element using outside connection projection electyrode and manufacturing method of semiconductor device using outside connection projection electrode |
KR1020070012548A KR100893559B1 (ko) | 2006-08-18 | 2007-02-07 | 반도체 소자의 실장 방법 및 반도체 장치의 제조 방법 |
CN200910141837.7A CN101562142B (zh) | 2006-08-18 | 2007-02-09 | 半导体元件的安装方法及半导体器件的制造方法 |
CN200710008067XA CN101127314B (zh) | 2006-08-18 | 2007-02-09 | 半导体元件的安装方法及半导体器件的制造方法 |
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US9010617B2 (en) * | 2011-01-10 | 2015-04-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Solder joint reflow process for reducing packaging failure rate |
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US4922377A (en) * | 1987-11-16 | 1990-05-01 | Hitachi, Ltd. | Module and a substrate for the module |
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US6039236A (en) * | 1997-06-11 | 2000-03-21 | Soltec B.V. | Reflow soldering apparatus with improved cooling |
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