TWI331385B - Mounting method of semiconductor element and manufacturing method of semiconductor device - Google Patents
Mounting method of semiconductor element and manufacturing method of semiconductor device Download PDFInfo
- Publication number
- TWI331385B TWI331385B TW096101591A TW96101591A TWI331385B TW I331385 B TWI331385 B TW I331385B TW 096101591 A TW096101591 A TW 096101591A TW 96101591 A TW96101591 A TW 96101591A TW I331385 B TWI331385 B TW I331385B
- Authority
- TW
- Taiwan
- Prior art keywords
- wiring board
- temperature
- semiconductor
- external connection
- semiconductor member
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 166
- 238000000034 method Methods 0.000 title claims abstract description 106
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 238000001816 cooling Methods 0.000 claims abstract description 95
- 238000010438 heat treatment Methods 0.000 claims abstract description 77
- 229910000679 solder Inorganic materials 0.000 claims description 81
- 239000010410 layer Substances 0.000 claims description 44
- 239000000463 material Substances 0.000 claims description 39
- 238000002844 melting Methods 0.000 claims description 23
- 230000008018 melting Effects 0.000 claims description 23
- 239000011229 interlayer Substances 0.000 claims 2
- 239000011368 organic material Substances 0.000 claims 2
- 238000007670 refining Methods 0.000 claims 1
- 230000008859 change Effects 0.000 description 17
- 238000012545 processing Methods 0.000 description 15
- 230000032798 delamination Effects 0.000 description 13
- 238000003780 insertion Methods 0.000 description 9
- 230000037431 insertion Effects 0.000 description 9
- 239000010949 copper Substances 0.000 description 8
- 239000000758 substrate Substances 0.000 description 8
- 238000012360 testing method Methods 0.000 description 8
- 238000010992 reflux Methods 0.000 description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052797 bismuth Inorganic materials 0.000 description 4
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 230000006378 damage Effects 0.000 description 4
- 230000004907 flux Effects 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000000155 melt Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000007613 environmental effect Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910000420 cerium oxide Inorganic materials 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 239000006184 cosolvent Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-M hydroxide Chemical compound [OH-] XLYOFNOQVPJJNP-UHFFFAOYSA-M 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920002577 polybenzoxazole Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000344 soap Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000013517 stratification Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05073—Single internal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13023—Disposition the whole bump connector protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81009—Pre-treatment of the bump connector or the bonding area
- H01L2224/8101—Cleaning the bump connector, e.g. oxide removal step, desmearing
- H01L2224/81011—Chemical cleaning, e.g. etching, flux
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
- H01L2224/81204—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding with a graded temperature profile
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/8121—Applying energy for connecting using a reflow oven
- H01L2224/81211—Applying energy for connecting using a reflow oven with a graded temperature profile
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30105—Capacitance
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
九、發明說明: 【發日月所之技術領域】 發明領域 本發明大體上係有關於半導體構件的安裝方法及半導 體裝置的製造方法,且更特別地係有關於一種經由不含鉛 (Pb)之外部連接凸出電極將半導體構件安裝在佈線板上之 半導體構件的安裝方法,以及一種半導體裝置之製造方法。 C先前技術:! 發明背景 從過去一直至現在已知的是,具有經由一不含鉛(pb) 之外部連接凸出電極以面向下的方式將一半導體構件覆晶 安裝在一佈線板之結構的半導體裝置稱為一無鉛的焊料凸 塊。 第1圖為一橫截面圖,其顯示施用至此一半導體裝置 之半導體構件的結構。第2圖係第1圖中由虛線所部份圍 繞的放大圖。 參照第1圖及第2圖’為製造該半導體構件,所謂的 晶圓加工係施用在矽(Si)所製造的半導體基材1上。諸如電 晶體之主動式元件及諸如電容器(未顯示)的被動式元件被 形成在該半導體基材1之主要表面上。此外,多層互連層3 係經由諸如二氧化矽(Si02)層2之絕緣層被設置在該半導 體基材1之另一主要表面上。 如第2圖所顯示,此一多層互連層3係藉由插入絕緣 薄膜5堆疊複數個鋁(A1)或銅(Cu)所製造的佈線層4而形 成。上方及下方的佈線層4係藉由一插入連接部件來連接。 該插入絕緣薄膜5的材料係所謂的低_κ材料,即為一 具有低介電常數的材料,所使用者諸如㈣璃摻雜敦之 FSG(摻雜氟的矽玻璃)、在矽玻璃加入碳之Si〇c,或一有 麟脂,使形成在佈線中之電氣電容減少且電氣信號的傳 送速度變高》 諸如形成在該半導體基材1上的主動元件或被動元件 之功能性元件雜衫層互連層3彼此連接,使執行所欲 功能之電子電路被形成。 複數個由鋁(A1)所製成的電極墊U係選擇性地設置在 該多層互連層3的上方,以與形成該多層互連層3的佈線4 連接。 一鈍態層6係選擇性地設置在該多層互連層3上。該 鈍態層6係由諸如氧化矽(Si〇2)或氮化矽(s取)之無機絕緣 材料製成。開口係選擇性地形成在該鈍態層6中使該等 電極墊11的中心部份被曝露。 此外’為了保護該半導體構件之表面,設置一有機絕 緣薄膜7以覆蓋該無機絕緣層6的上表面以及在電極墊u 上的無機絕緣層6之邊緣表面。 有機絕緣薄膜7的材料係選自於諸如聚醯亞胺、bCb (苯并環丁烯)、酚樹脂或聚苯并噁唑之有機絕緣材料。 由例如鈦(Ti)/銅(Cu)所製造的UBM(凸塊底層金屬)8 係被設置在該電極塾11的上表面。UBM 8以一垂直方向由 無機絕緣層6及有機絕緣薄膜7不被設置的電極墊u之一 部份上表面至稍微在有機絕緣薄膜7之上表面的上方處被 設置。UBM 8覆蓋該有機絕緣薄膜7的端部表面。 具有實質上球狀構形的外部連接凸出電極9被設置在 該UBM 8的上表面。稱為焊料塊之外部連接凸出電極9係 由諸如錫(Sn)-銀(Ag)或包含銅(Cu)的錫(811)_銀(Ag)之不含 鉛(Pb)的焊料所製造。 第3圖為一橫截面圖,其顯示第】圖所示的半導體構 件10以面向下的方式被覆晶安裝在一佈線板上的狀態。參 照第3圖,該半導體構件10係以面向下的方式被覆晶安裝 在一佈線板20上。 該佈線板20係為一由例如玻璃環氧化物材料或聚醯亞 胺帶所製成的有機組裝板。在該佈線板2〇的上表面,複數 個電極墊21被選擇性的設置且焊料抗蝕層22選擇性的設 置開口’使該等電極墊21的中心部份被曝露。 該等外部連接凸出電極9被連接至設置在佈線板2〇上 的電極墊21。此外,所謂的底層材料23係被設置在該半導 體構件10及佈線板20之間,複數個由焊料所製造的外部 連接凸出電極24係被設置在該佈線板2〇的下方表面。 具有此一結構之半導體裝置係藉由下述步驟所製造。 首先,該半導體構件10係以面向下的方式覆晶安裝在 該佈線板20上。 隨後,藉由回流加熱方法,外部連接凸出終端9以及 預先設置在佈線板20的電極墊21上之預焊料(焊料預塗覆) 係被熔化’使半導體構件10之外部連接凸出終端9與佈線 1331385 板20連接。該預焊料不含鉛(pb)。 後來’該底層材料23係被供應在該半導體構件1〇及 該佈線板20之間’且隨後被固化。 最後’焊料球被設置在該佈線板2〇的下表面,使外部 5連接凸出電極24藉由一回流加熱方法及一冷卻方法被連 接。 同時’日本早期公開專利申請案第2006-111898號揭 示一種具有下述結構的電子組份。即,在一皁金屬上之鍍 錫薄膜係在室溫下經氧化或水合處理,一氧化物或氫氧化 10物的表面層係被形成在該鍍錫薄膜的表面,使該表面層變 稠密且均勻,且抑制錫鬚晶的生長。 再者’曰本早期公開專利申請案第11-354919號揭示 一種電子電路板的製造方法,其中一電子組件及電路板係 利用包含鉍(Bi)的無鉛(Pb)焊料連接。在此方法中,該焊料 15係在大約1〇-2〇艺/S的冷卻速度下被冷卻,使該電子組件 及該電路板被連接。 此外’國際專利公開案(International Patent Publication) 第2004/047167號揭示一種半導體裝置,其中一貫穿電極 係被形成在一佈線板中,以電氣連接形成在佈線板之底部 20 基材的佈線板形成表面上,其中在佈線板上一半導體晶片 係被覆晶安裝且一電極係被形成在晶片安裝表面;且該底 部基材之熱膨脹係數係相等於該半導體晶片之熱膨脹係 數,或小於該佈線層之熱膨脹係數。 如上所述,在製造該半導體裝置時,其中該半導體構 8 件10係藉由回流加熱方法以不包含鉛(Pb)的外部連接凸出 電 被覆晶安裝在該佈線板20上,該等外部連接凸出終 ^及該不&含錄(Pb)且預先被S置在該佈線板20的電極 墊21上之預焊料(焊料預塗覆)係被熔化,使該半導體構件 卜。P連接凸出終端9及該佈線板2〇被連接。隨後,該 等外。P連接凸出終端9及預焊料係被冷卻以成為固體。 。亥半導體構件1〇之矽基材的熱膨脹係數為大約3至4 ppm/C。在另一方面,由一有機金屬板所製造的佈線板2〇 之熱膨脹係數為大約1〇至17 ppmrc。因此佈線板2〇之 熱膨脹係數為係大於該半導體構件1〇之熱膨脹係數。 此外,該等外部連接凸出終端9及預焊料係由不包含 鉛(Pb)之焊料所製成。若該等外部連接凸出終端9及預焊料 係由例如錫(Sn)·銀(Ag)所形成的焊料或錫(Sn)-銀(Ag)-銅 (Cu)所形成的焊料所製成’該焊料的熔點為大約217至220 t。 因此,在該焊料被加熱至比諸如25〇。(:的熔點還要高的 溫度時,該焊料會熔化,且由於該半導體構件1〇及該佈線 板20的熱膨脹而流動變形。 在該回流加熱方法中’半導體構件10被設置的佈線板 20被移動至一回流加工裝置中,其中具有加熱器之複數的 加熱區域(區塊)係被排列成一條線,以被加工。在回流加工 裝置中每個加熱區域中之該等加熱器的溫度係被控制以使 該加熱方法及溫度降低方法(即冷卻方法)被執行。 第4圖為一曲線圖,顯示在一用於連接半導體構件1〇 1331385 之外部連接&出電極9及佈線板20之回流加熱方法中以及 在該回流加熱方法之後大約〇·7 〇c/s之冷卻速度下之冷卻 方法中第3圖所顯示之半導體裝置的溫度變化。該圖的水 平軸指示時間(sec)且垂直軸指示溫度(。〇。 5 換言之’在該回流加熱方法中,大約150。(:的溫度係 被維持一指定的時間。助溶劑係被活化且在該等外部連接 凸出終端9及預焊料之表面的氧化物薄膜係被移除。隨後, 加熱直到溫度大於該焊的熔點,諸如250。〇。 在該焊料被熔化之後,停止加熱或將溫度降低至相等 10或低於該焊料的熔點(217至220。〇,且藉此該焊料係被固 化。在該焊料被固化之後,由該焊料之熔點逐漸冷卻至接 近室溫的溫度。 在相關的技藝中’製造步驟的效率大約0.7 °C/s係被 施用作為一冷卻速度。如上所述,不含有鉛(pb)的焊料之熔 15點係高於含有鉛(Pb)的焊料之熔點。因此,為有效的冷卻至 接近正常的溫度’在相關技藝中係施用約0.7 °c/s的冷卻 速度。 然而’若該半導體裝置在約〇.7 °C/s的冷卻速度下被 冷卻,基於半導體構件10及佈線板2〇之間熱膨脹係數的 20差異,張力/壓力明顯地被產生。換言之,由於佈線板20 之熱膨脹係數大於半導體構件1〇的熱膨脹係數,由於冷卻 過程時該半導體構件10之溫度改變,壓力由具有較大膨脹 及收縮的佈線板20被施加。 由於此一狀態係在該焊料(該等外部連接凸出終端9及 10 1^31385 該預焊料)被固化時產生,該焊料不可能會吸收由該佈線板 20施加至該半導體構件10上的壓力。因此,由該佈線板 20施加至該半導體構件10的壓力可能會被施加至由多層 佈線層3之低-K材料所製造的插入絕緣薄膜5。 5 由於此一原因,藉由該等插入絕緣薄膜5彼此堆疊之 佈線層4的分層可被產生’使電氣缺陷可能發生於該半導 體裝置中。
【發明内容:J 發明概要 10 因此,本發明之具體實施例可提供一種新穎的且有用 的安裝半導體構件的方法及一種製造一半導體裝置的方 法,藉此解決上述一或多個問題。 更特別的是,本發明之具體實施例可提供一種半導體 構件之安裝方法以及半導體構件之製造方法,藉此當該半 15導體構件藉由一不含有鉛(Pb)之外部連接凸出終端被安裝 在一佈線板上時,由該佈線板施加至包含以低·κ材料所形 成之插入絕緣薄膜的半導體構件之一多層佈線部份的壓力 可被減輕,可防止分層且增進半導體裝置之製造產量。 本發明之一方面可提供一種半導體構件的安裝方法, 20 藉此該半導體構件經由一不含鉛(Pb)的外部連接凸出電極 安裝在一佈線板上,該安裝方法包括施用一回流加熱方法 以連接半導體構件之外部連接凸出電極以及佈線板,且隨 後以相等或低於0.5°C/s的冷卻速度冷卻經連接的半導體 構件及佈線板之步驟。 11 1331385 本發明之另一方面可提供一種半導體構件的安裝方 法’糟此半導體構件經由一外部連接凸出電極被安裝在一 佈線板上,該安裝方法包括施用一回流加熱方法以連接半 導體構件之外部連接凸出電極以及佈線板,且隨後施用一 5 階段式冷卻(step-cooling)方法之步驟;其中,在該階段式冷 卻方法中,該經連接的半導體構件及佈線板被冷卻,使溫 度下降;當溫度到達一指定的溫度之後,該指定的溫度係 被維持一指定的時間;當該指定的時間過後,半導體構件 及佈線板被再次冷卻,使溫度被進一步降低。在上述半導 10 體構件的安裝方法中,該階段式冷卻方法可被重覆一或多 次。該指定的溫度可相等或大於約8〇 °c以及相等或低於約 150 C。該指定的時間可相等或大於12〇秒。 本發明之另一方面可提供一種半導體裝置的製造方 法,其包括施用一回流加熱方法以連接佈線板以及半導體 15構件之不含錯(Pb)的外部連接凸出電極’且隨後以相等或低 於0.5 C/s的冷卻速度冷卻該半導體構件及佈線板之步驟。 本發明之另一方面可提供一種半導體裝置的製造方 法,其包括施用一回流加熱方法以連接半導體構件之外部 連接凸出電極以及佈線板’且隨後施用一階段式冷卻方法 20之步驟;其中,在該階段式冷卻方法中,該經連接的半導 體構件及佈線板被冷卻’使溫度下降;當溫度到達一指定 的溫度之後’該指定的溫度係被維持—指定的時間;當該 指定的時間過後’半導體構件及佈料被再次冷卻,使溫 度被進一步降低。 12 晉之述的半導體構件之安裝方法或上述的半導體裝 方法,當該半導體構件經由1含輝b)的外部連 t凸㈣端被安裝在一佈線板上時,由該佈線板施加在包 、低K材料所形成之插人絕緣薄膜的半導體構件之多 層佈線部份的壓力可被減少,使分層可被防止且半導體裝 置的製造產量可被改善。 本發明之其他的目的、特徵及優點將藉由詳細描述並 參照所附圖式及而被更進—步的被了解。 圖式簡單說明 第1圖為-橫截面圖’顯示—半導體構件之結構; 第2圖為第1圖中虛線所圍繞的部份之放大圖; 第3圖為一橫截面圖,顯示第1圖所顯示的半導體構 件被覆晶安裝在一佈線板的狀態; 第4圖為一曲線圖,顯示第3圖中所顯示的半導體裝 置在一回流加熱方法中以及§亥回流加熱方法之後以約ο.? °C/s的冷卻速度之冷卻方法中的溫度變化; 第5圖為一曲線圖’顯示第3圖中的半導體裝置在一 回流加熱方法中以及該回流加熱方法之後以約0.5。(:/s的 冷卻速度之冷卻方法中的溫度變化; 第6圖為一曲線圖’顯示第3圖中的半導體裝置在一回 流加熱方法中以及該回流加熱方法之後以約0.3 t:/s的冷 卻速度之冷卻方法中的溫度變化; 第7圖為一曲線圖,顯示第3圖中的半導體裝置在一 回流加熱方法中以及該回流加熱方法之後的冷卻方法(第 1331385 -階段式冷部方法)中的溫度變化;以及 第8圖為#線圖’顯示第3圖中的半導體裝置在—回 抓加熱方法中β及該回流加熱方法之後的冷卻方法(第二 階段式冷卻方法)中的溫度變化。 5 【實施方式】 較佳實施例之洋細說明 參知、第5圖至第8圖及下方的内容,描述本發明之具體 實施例。 本發月之具體實施例係有關於一回流加熱方法,以及 10該回流加熱方法之後的冷卻方法。在本文中,回流加熱方 法被施用於第1圖至第3圖所討論的方法中,藉此,該半導 體構件10,,.至由不含錯(Pb)之所謂的無叙㈣的焊料被覆晶 安裝在該佈線板20上,以在該半導體構件1〇被覆晶安褒在 該佈線板20上之後連接半導體構件1〇之外部連接凸出電極 15 9以及佈線板20。 更特別的疋,在外部連接凸出終端9以及預先設置在佈 線板20的電極独上之不含有紹㈣的預焊料(焊料㈣ 覆,未顯示)係藉由-回流加熱方法被炫化,使其等彼此連 接’當該焊料被冷卻並固化,且該半導體裝置被冷卻至接 近常溫時,本發明之第-具體實施例或第二具體實施例被 施用作為冷卻的方法。 藉此-方法’該焊料由回流加熱方法之後的冷卻方法 而被固化’且該半導體裝置被冷卻至接近常溫基於半導 體構件10及佈線板20之熱膨脹係數之間的差異所產生的壓 14 1331385 力,即,由佈線板2〇施加至半導體構件之10多層佈線層3的 壓力會被抑制,使該多層佈線層3的分層不被發生。 在下述内容中,由於半導體構件10及佈線板20的結構 與第1圖至第3圖中所討論的相同,故,省略相關的描述。 5 本發明的發明人發現藉由逐步地減少冷卻的速度, 即,逐步地延遲溫度到達一指定的冷卻溫度之時間,可以 解決上述問題。 [本發明之第一具體實施例] 本發明之第一具體實施例中,一冷卻方法係藉由設定 10 比習知約0.7 °C/s還要低的冷卻速度,即,約〇·5 °c/s,逐 漸冷卻來實施。 第5圖為一曲線圖’顯示第3圖中的半導體裝置在連接 半導體構件10之外部連接凸出電極9及佈線板20的回流加 熱方法中,以及該回流加熱方法之後約05。〇/8的冷卻速度 15之冷卻方法中的溫度變化。該圖中的水平軸表示時間(秒) 且垂直轴表示溫度(°C)。 換言之,在該回流加熱方法中,約15〇 〇c的溫度被維 持一段指定的時間。助熔劑係被活化且在外部連接凸出終 端9之表面上之氧化物薄膜以及預焊料被移除。隨後,加熱 20 直到溫度大於該焊料的溶點,例如250 °C。 當回流加熱方法開始之後,且經過約24〇秒時,溫度到 達約250 C。此時,該焊料係炫化。該焊料熔化之後,停 止加熱且溫度降低至相等或低於該焊料的熔點(217至22〇 °C),藉此該焊料被固化。在該焊料被固化之後,逐漸由該 15 1331385 焊料之熔點冷卻至一接近常溫的溫度。 在本發明之第一具體實施例中,施用的冷卻速度為約 0.5 °C/s。 因此,如第5圖所顯示,當回流加熱方法開始之後,旯 5 經過約650秒時,溫度到達約50 °C。 在溫度到達約50 °C之後,連接至該佈線板2〇的該半導 體構件10係被拿到回流加工裝置之外,以自行冷卻(自然 冷卻)。 隨後,該底層材料23被設在該半導體構件10及該佈線 10 板20之間,且隨後被固化。最後,焊料球被設置在該佈線 板20的下表面,使外部連接凸出電極24被連接。 [本發明之第二具體實施例] 在本發明之第二具體實施例中,一冷卻方法係藉由設 定比習知約0.7 °C/s還要低的冷卻速度,即,約〇 3 °C/s, 逐漸冷卻來實施。 第6圖為一曲線圖,顯示第3圖中的半導體裝置在連接 半導體構件10之外部連接凸出電極9以及佈線板20之回流 加熱方法中’以及該回流加熱方法之後約0.3 t/s的冷卻速 度之冷卻方法中的溫度變化。該圖中的水平軸表示時間 20 (秒)且垂直轴表示溫度(。〇。 換言之,在該回流加熱方法中,約150。(:的溫度被維 持一段指定的時間。助熔劑係被活化且在外部連接凸出終 端9之表面上之氧化物薄膜以及預焊料被移除。隨後,係施 加熱直到溫度大於該焊料的熔點,例如250 °C。 16 1331385 當回流加熱方法開始之後,且經過約240秒時,溫度到 達約250 °C。此時,該焊料係熔化。該焊料熔化之後,停 止加熱且溫度降低至相等或低於該焊料的熔點(217至22〇 C) ’藉此該焊料被固化。在該焊料被固化之後,逐漸由該 5焊料之熔點冷卻至一接近常溫的溫度。 在本發明之第二具體實施例中,施用的冷卻速度為約 0·3 °C/s。 因此,如第6圖所顯示,當回流加熱方法開始之後,且 經過約880秒時,溫度到達約50。(:。 10 在溫度到達約50 °C之後’連接至該佈線板20的該半導 體構件10係被拿到回流加工裝置之外,以自行冷卻(自然 冷卻)。 隨後,該底層材料23被設在該半導體構件10及該佈線 板20之間,且隨後被固化。最後,焊料球被設置在該佈線 15 板20的下表面,使外部連接凸出電極24被連接。 本發明之發明人檢查由上述本發明之具體實施例所製 造的半導體裝置之半導體構件1〇的多層佈線層3。發明人發 現在由低-K材料所製造的插入絕緣薄膜5所堆疊的佈線層4 並沒有分層。 20 發明人還在JEDEC(聯合電子裝置工程會議(Joint
Electron Device Engineering Council))·第3級所設定的環境 下執行100次的溫度衡擊測試作為環境測試、濕氣吸收測 試,以及回流測試三次。結果’發明人發現諸如由於施加 在由低-K材料所製造的插入絕緣薄膜所堆疊的佈線層4的 17 壓力所產生的分層並不會發生β 因此,藉由設定比習知約0·7 °C/s還要低的冷卻速度, 即’約0.5 °C/s或0.3 °C/s,可以防止基於伴隨冷卻之半導 體構件10及佈線板20的收縮或變形,由佈線板2〇施加在半 5導體構件10上之壓力的發生。 因此,自佈線板20施加在由低-K材料所製造的插入絕 緣薄膜5所堆疊的佈線層4的壓力會被減輕,使諸如分層之 破壞被防止。 [本發明之第三具體實施例] 10 在上述所討論的本發明之第一及第二具體實施例中, 在回流加熱方法之後的冷卻方法中,藉由降低冷速度,在 半導體構件10之多層佈線層3中自佈線板20施加在由低-K 材料所製造的插入絕緣薄膜5的壓力會被減輕,使諸如分層 之破壞被抑制。 15 然而,在該等具體實施例中,當冷卻速度被降低的更 多,則冷卻的時間會變長,使該半導體裝置的製造成本增 加。 因此,在本發明之第三具體實施例中,冷卻速度以分 階段的方式變化,即,以一階段式的方法冷卻,使用於冷 2〇 卻方法的時間在沒有激烈的溫度變化的情況下被縮短。由 於激烈的溫度變化沒有發生’施加在由半導體構件丨〇之低 -K材料所製造的插入絕緣薄膜5所堆疊之佈線層4的壓力會 被減輕,使諸如分層之破壞被抑制,且可防止冷卻時間變 長0 18 1331385 更特別的是,在回流加熱方法之後的冷卻方法期間, 溫度被維持在一指定的溫度一段特定的時間’且隨後再次 被降低。在該冷卻方法中’此階段式方法被執行至少一次, 使該半導體裝置被冷卻至約50 °C。 5 第7圖為一曲線圖,顯示第3圖中的半導體裝置在連接 半導體構件10之外部連接凸出電極9以及佈線板20之回流 加熱方法中,以及該回流加熱方法之後的冷卻方法(第一 step-冷卻方法)中的溫度變化。該圖中的水平轴表示時間 (秒)且垂直軸表示溫度(°C)。 10 換言之’在該回流加熱方法中,約150 °C的溫度被維 持一段指定的時間。助熔劑係被活化且在外部連接凸出終 端9之表面上之氧化物薄膜以及預焊料被移除。隨後,加熱 直到溫度大於該焊料的熔點,例如25〇 t。 當回流加熱方法開始之後,且經過約24〇秒時,溫度到 15達約250 c。此時,該焊料係熔化。該焊料熔化之後,停 止加熱且溫度降低至相等或低於該焊料的熔點(217至22〇 C),藉此該焊料被gj化。在該焊料被固化之後 ,逐漸由該 焊料之熔點冷卻至一接近常溫的溫度。 在本發明之第二具體實施例中,施用的冷卻速度為約 〇 0.7 C/S β該回流加熱方法開始之後約彻秒時,溫度被 維持在約150 °C約30〇秒。 隨後,以約0.7 C/s執行冷卻,直到溫度到達約5〇 〇c。 因此如第7圖所不’當該回流加熱方法開始之後約81〇 秒時,溫度到達約50 。 19 1331385 在溫度到達約50 °C之後,連接至佈線板20之半導體構 件10係被拿到回流加工裝置之外,以自行冷卻(自然冷卻 隨後’該底層材料23被設在該半導體構件10及該佈線 板20之間,且隨後被固化。最後,焊料球被設置在該佈線 5板20的下表面,使外部連接凸出電極24被連接。 [本發明之第四具體實施例] 在本發明之第三及四具體實施例中,於回流加熱方法 ^ 之後的冷卻方法期間,溫度被維持在一指定溫度一特定的 時間,且隨後再次降溫。至少執行一次冷卻方法,使該半 10導體裝置被冷卻至約50 °C。 第8圖為一曲線圖,顯示第3圖中的半導體裝置在連接 半導體構件10之外部連接凸出電極9與佈線板2〇之回流加 熱方法,以及該回流加熱方法之後的冷卻方法(第二階段式 冷卻方法)中的溫度變化。該圖中的水平轴表示時間(秒) 15 且垂直軸表示溫度(。〇。 • 換言之,在該回流加熱方法中,約150 °C的溫度被維 持—段指定的時間。助熔劑係被活化且在外部連接凸出終 端9之表面上之氧化物薄膜以及預焊料被移除。隨後,加熱 直到溫度大於該焊料的熔點,例如25〇 。 當回流加熱方法開始之後,且經過約24〇秒時,溫度到 達約250 c。此時,該焊料係炫化。該焊料炫化之後,停 止加熱且溫度降低至相等或低於該焊料的熔點(2口至22〇 C) ’藉此該焊料被固化。在該焊料被固化之後逐漸由該 焊料之熔點冷卻至一接近常溫的溫度。 20 1331385 在本發明之第四具體實施例中,施用的冷卻速度為約 0.7 °C/s。當該回流加熱方法開始之後約460秒時溫度到達 120 °C,且被維持在約120。(:約300秒。 隨後’以約0_7它/s執行冷卻,直到溫度到達約50。(3。 5 因此,如第8圖所示,當該回流加熱方法開始之後約860 秒時,溫度到達約50。(:。 在溫度到達約50 〇C之後,連接至佈線板20之半導體構 件10係被拿到回流加工裝置之外,以自行冷卻(自然冷卻)。 隨後,該底層材料23被設在該半導體構件10及該佈線 10 板20之間’且隨後被固化。最後’焊料球被設置在該佈線 板20的下表面,使外部連接凸出電極24被連接。 在顯示於第7圖及第8圖之本發明第三及四具體實施例 中’維持一指定的溫度(在顯示於第7圖中之第三具體實施 例為約150 °C,或在顯示於第8圖中之第四具體實施例為約 15 120 °c)在該回流加工裝置中被實施。然而,本發明並不僅 限於此實施例。 例如,在溫度到達此一指定溫度之後(在顯示於第7圖 中之第二具體實施例為約150 °C,或在顯示於第8圖中之第 四具體實施例為約120。〇,該半導體構件10及該佈線板2〇 20可由該回流加工裝置被移到一恆溫室t,使溫度可在該恆 溫室中維持該指定溫度。 在此一實施例中,在溫度到達約50 t之後,連接至佈 線板20之半導體構件10係被拿到恆溫室之外,以自行冷卻 (自然冷卻)。 21 1331385 本發明之發明人檢查由上述本發明之具體實施例所製 造的半導體裝置之半導體構件10的多層佈線層3。發明人發 現在由低-K材料所製造的插入絕緣薄膜5所堆疊的佈線層4 並沒有分層。 5 發明人還在JEDEC(聯合電子裝置工程會議(Joint
Electron Device Engineering Council))-第3級所設定的環境 下執行100次的溫度衝擊測試作為環境測試、濕氣吸收測 試’以及回流測試三次。結果,發明人發現諸如由於施加 在由低-K材料所製造的插入絕緣薄膜所堆疊的佈線層4的 10 壓力所產生的分層並不會發生。 一般來說,固定的張力可因壓力的作用而產生,且若 此壓力被維持則該壓力會因螺變現象(creep phenomenon) 被減輕。 在此實施例中,考量至此一螺變現象,在該回流加熱 15 方法之後的冷卻方法中,一指定的溫度被維持一指定的時 間。在溫度被再次下降之後,使該冷卻的速度以一階段式 的方法變化。 因此,伴隨該冷卻方法,焊料可隨著該半導體構件1〇 及佈線板20收縮及變形,使由該佈線板施加至該半導體構 20 件的壓力被吸收。因此,由佈線板20施加在由低-K材料所 製造的插入絕緣薄膜5所堆疊的佈線層4的壓力被減少,使 諸如分層之破壞被防止。 此外’同時冷卻時間可能很長,在本發明之第一或第 二具體實施例中’藉由使冷卻速度變低,會使製造成本増 22 1331385 加’在本發明之第三具體實施射不需要使冷卻速度變 慢,該加工時間可以縮短。 孤度最好〇又疋在約80至i50〇c的範圍内,該溫度係作為 一欲被維持的指定溫度。 5 本發明的發明人發5見,若欲被維持的溫度低於約8〇 °c,壓力會在該指定溫度被維持的同時被施加至藉由插入 絕緣薄膜5所堆疊的佈線層4上,因而發生分層。 此外’若欲被維持的溫度高於約150。(:時,即使分層 被防止,當溫度高於約150 〇c時,焊料會再次由於冷卻以 10及由該佈線板20施加至半導體構件1〇的壓力無法被吸收而 變形。故,分層無法被防止。因此,由於此一原因,當溫 度相等或低於約15〇°C時,必需以階段式的方法改變溫度。 因此’較佳地’設定一溫度至約80至150 t的範圍内, 以該溫度為欲被維持的指定溫度。 15 糾,較佳地,維持該指定溫度的時間等於或大於約 120 秒。 若維持該指定溫度的時間短於約丨2 〇秒,基於蠕變現象 在壓力被減少之前進行冷卻,且藉此該焊料無法吸收由佈 線板20施加至半導體構件1〇㈣力,且分層無法被防止。 10 在另一方面’若維持指定溫度的時間相等或大於約 120秒,由佈線板20施加至半導體構件1〇的壓力可被充分地 減少。’伴隨該冷卻方法,焊料可隨著豸半導體構件 10及佈線板20收縮及變形,使由該佈線板施加至該半導體 構件的壓力被吸收。因此,由佈線板2〇施加在由低_κ材料 23 1331385 所製造的插入絕緣薄膜5所堆疊的佈線層4的壓力被減少, 使諸如分層之破壞被防止。 因此’由防止諸如分層之破壞的觀點來看,較佳地, 維持才曰疋溫度的時間較長。然而,若維持指定溫度的時間 5太長,加工時間會變得更長’使製造成本增加。因此,維 持溫度的時間上限係基於加工時間的上限而被設定。 維持指定溫度一指定時間且隨後再次降低溫度的步驟 數目在此實施例中並不限為一次,而可以是多次的。由防 止諸如分層之破壞的觀點來看,較佳地,該等步驟的數目 10為較多的。然而,若該等步驟的數目為太多,加工時間會 變得更長,使製造成本增加。因此,該等步驟之數目的上 限係基於加工時間的上限而被設定。 因此,在本發明之第三或第四具體實施例中,冷卻速 度係階段式被改變。由於此一原,在本發明之第三或第四 15具體實施例以及第一或第二具體實施例中,由佈線板20施 加在由半導體構件1〇之低_K材料所製造的插入絕緣薄膜5 所堆疊的佈線層4的壓力被減少,使諸如分層之破壞可被防 止。此外,加工時間可被縮短。 因此,如上所述,根據本發明之實施例,當該半導體 20 構件經由一不含鉛(Pb)的外部連接凸出终端被安裝在一佈 線板上時,由該佈線板施加在包括由一低·κ材料所形成的 插入絕緣薄膜之半導體構件的多層佈線部件的壓力可被減 少’使分層可被防止。 此外’根據本發明之具體實施例,一低價的有機組裝 24 1331385 板可被用來料佈線板。a此,可以節省製造成本。 再者,根據本發明之具體實施例,為防止上述之當半 導體構件被安裝在佈線板時的分層,不需要施用特定的結 構在s亥半導體構件及該佈線板,且不需要使用一特定的安 5裝裝置。因此,當半導體構件被安裝在佈線板時在該半導 體構件中的分層可輕易地被防止。 本發明並不限於該4具體實施例’且本發明之變化及 修改也不偏離本發明所欲保護之範圍。 本發明係基於2006年8月18曰所提申的日本優先權專 1〇 利申請案第2006-223280號’該申請案之全部内容皆併入本 案作為參考文獻。 t圖式簡單說明3 第1圖為一橫截面圖,顯示一半導體構件之結構; 第2圖為第1圖中虛線所圍繞的部份之放大圖; 15 第3圖為一橫截面圖,顯示第1圖所顯示的半導體構 件被覆晶安裝在一佈線板的狀態; 第4圖為一曲線圖,顯示第3圖中所顯示的半導體裝 置在一回流加熱方法中以及該回流加熱方法之後以約〇·7 °C/S的冷卻速度之冷卻方法中的溫度變化; 20 第5圖為一曲線圖,顯示第3圖中的半導體裝置在一 回流加熱方法中以及該回流加熱方法之後以約〇.5 °C/s的 冷卻速度之冷卻方法中的溫度變化; 第ό圖為―曲線圖,顯示第3圖中的半導體裝置在一回 流加熱方法中以及該回流加熱方法之後以約〇.3 /s的冷 25 1331385 卻速度之冷卻方法中的溫度變化; 第7圖為一曲線圖,顯示第3圖中的半導體裝置在一 回流加熱方法中以及該回流加熱方法之後的冷卻方法(第 一階段式冷卻方法)中的溫度變化;以及 第8圖為一曲線圖,顯示第3圖中的半導體裝置在一回 流加熱方法中以及該回流加熱方法之後的冷卻方法(第二 階段式冷卻方法)中的溫度變化。 【主要元件符號說明】
1 半導體基材 2 二氧化石夕(Si02)層 3 多層互連層 4 佈線層 5 插入絕緣薄膜 6 鈍態層 7 有機絕緣薄膜 8 UBM 9 外部連接凸出電極 10 半導體構件 11 電極墊 20 佈線板 21 電極墊 22 焊料抗钱層 23 底層材料 24 外部連接凸出電極 26
Claims (1)
1331385 -•5—9-專 06 J 28 日 第96101591號專利申請案申請專利範圍 十、申請專利範圍: . 1. 一種半導體構件的安裝方法,藉此該半件係 一不含鉛(Pb)的外部連接凸出電極被安裝在一佈線板 上,該安裝方法包含: ' 5 施用一回流加熱方法以連接該半導體構件之外部 • 連接凸出電極與該佈線板直到形成該外部連接凸出電 極之一材料被炼化; 冷卻該半導體構件及佈線板使得一溫度成為相等 或低於形成該外部連接凸出電極之該材料的熔點,且形 10 成該外部連接凸出電極之該材料被固化;以及 在形成該外部連接凸出電極之該材料被固化後,以 一相等或低於0.5 °c/s之冷卻速度,逐漸地將該經連接 的半導體構件及佈線板冷卻達數百秒,直到該溫度成為 接近正常室溫的溫度。 15 2.如申請專利範圍第1項之半導體構件的安裝方法,其中 該冷卻速度為約0.5 °C/s。 3. 如申請專利範圍第1項之半導體構件的安裝方法,其中 該外部連接凸出電極係由不含鉛(Pb)的焊料製成。 4. 如申請專利範圍第1項之半導體構件的安裝方法,其中 20 該佈線板係以一有機材料製成。 5. 如申請專利範圍第4項之半導體構件的安裝方法,其中 該半導體構件包括一多層佈線結構,其中佈線層係經由 以具有低介電常數之材料所製造的層間絕緣薄膜來堆 疊。 27 1331385 . 6.-種半導體構件之絲方法,藉此該半導體構件係經由 .一外°卩連接凸出電極被安裝在一佈線板上,該安裝方法 包含: 施用—回流加熱方法以連接該半導體構件之外部 5 連接凸出電極與該佈線板,且接著在形成該外部連接凸 出電極之一材料被固化後,從形成該外部連接凸出電極 之材料的熔點到一接近正常室溫的溫度間施用階段式 冷卻方法之步驟; • 其115 ’在該卩冑段式冷卻方法中, 10 該經連接的半導體構件及該佈線板被冷卻,使溫度 降低; & 在溫度到達一指定溫度之後,該指定溫度被維持一 指定時間; 在經過該指定時間之後,該半導體構件及該佈線板 15 被再次冷卻,使溫度更進一步降低。 φ 7·如申請專利範圍第6項之半導體構件之安裝方法,其中 該階段式冷卻方法被重覆一或多次。 8·如申請專利範圍第6項之半導體構件之安裝方法,其中 該指定的溫度係相等或大於約80。(:,且相等或低於約 20 150。(:。 9. 如申請專利範圍第6項之半導體構件之安裝方法,其中 該指定時間係相等或大於120秒。 10. 如申請專利範圍第6項之半導體構件之安裝方法,其中 該指定時間係相等或大於3〇〇秒。 28 !331385 11. 如申請專利範圍第6項之半導體構件之安裝方法,其中 該外部連接凸出電極係以不含鉛(Pb)的焊料製成。 12. 如申請專利範圍第6項之半導體構件之安裝方法,其中 該佈線板係以一有機材料製成。 5 13.如申請專利範圍第12項之半導體構件之安裝方法,其 中該半導體構件包括一多層佈線結構,其中佈線層係經 由以具有低介電常數之材料所製造的層間絕緣薄膜來堆 • 疊。 14. 一種半導體裝置之製造方法,包含: 10 施用一回流加熱方法以連接一佈線板與一半導體構 件之不含鉛(Pb)的外部連接凸出電極直到形成該外部連 接凸出電極之一材料被熔化; 冷卻該半導體構件及佈線板使得一溫度成為相等或 低於形成該外部連接凸出電極之該材料的熔點,且形成 15 該外部連接凸出電極之該材料被固化;以及 Φ 在形成該外部連接凸出電極之該材料被固化後,以 一相等或低於0.5 °C/s之冷卻速度,逐漸地將該半導體 構件及佈線板冷卻達數百秒,直到該溫度成為接近正常 室溫的溫度。 2〇 15. —種半導體裝置之製造方法,包含: 施用一回流加熱方法以連接一半導體構件之外部連 接凸出電極與一佈線板,且接著在形成該外部連接凸出 電極之一材料被固化後,從形成該外部連接凸出電極之 材料的熔點到一接近正常室溫的溫度間施用階段式冷卻 29 1331385 方法之步驟; 其中,在該階段式冷卻方法中, 該經連接的半導體構件及該佈線板被冷卻,使溫度 降低; 5 在溫度到達一指定溫度之後,該指定溫度被維持一 指定時間; 在經過該指定時間之後,該半導體構件及該佈線板 被再次冷卻,使溫度更進一步降低。
30
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006223280A JP4946262B2 (ja) | 2006-08-18 | 2006-08-18 | 半導体素子の実装方法及び半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200812032A TW200812032A (en) | 2008-03-01 |
TWI331385B true TWI331385B (en) | 2010-10-01 |
Family
ID=39095295
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW096101591A TWI331385B (en) | 2006-08-18 | 2007-01-16 | Mounting method of semiconductor element and manufacturing method of semiconductor device |
Country Status (5)
Country | Link |
---|---|
US (1) | US7879713B2 (zh) |
JP (1) | JP4946262B2 (zh) |
KR (1) | KR100893559B1 (zh) |
CN (2) | CN101562142B (zh) |
TW (1) | TWI331385B (zh) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010040599A (ja) * | 2008-07-31 | 2010-02-18 | Sanyo Electric Co Ltd | 半導体モジュールおよび半導体装置 |
DE112010001560B4 (de) * | 2009-04-08 | 2020-08-13 | Efficient Power Conversion Corporation | GaN-FLIP-CHIP-Leistungstransistor mit elektrisch isolierter Rückseite |
US9010617B2 (en) | 2011-01-10 | 2015-04-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Solder joint reflow process for reducing packaging failure rate |
JP5853135B2 (ja) * | 2012-03-15 | 2016-02-09 | パナソニックIpマネジメント株式会社 | 電極接合方法および回路部材接合ライン |
JP6197619B2 (ja) * | 2013-12-09 | 2017-09-20 | 富士通株式会社 | 電子装置及び電子装置の製造方法 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4922377A (en) * | 1987-11-16 | 1990-05-01 | Hitachi, Ltd. | Module and a substrate for the module |
JPH02229858A (ja) * | 1988-11-12 | 1990-09-12 | Kureha Chem Ind Co Ltd | 電子部品封止用樹脂組成物および封止電子部品 |
JP2966972B2 (ja) * | 1991-07-05 | 1999-10-25 | 株式会社日立製作所 | 半導体チップキャリアとそれを実装したモジュール及びそれを組み込んだ電子機器 |
JP3215008B2 (ja) * | 1995-04-21 | 2001-10-02 | 株式会社日立製作所 | 電子回路の製造方法 |
JP2793528B2 (ja) * | 1995-09-22 | 1998-09-03 | インターナショナル・ビジネス・マシーンズ・コーポレイション | ハンダ付け方法、ハンダ付け装置 |
JP3629345B2 (ja) * | 1996-12-12 | 2005-03-16 | 新光電気工業株式会社 | フリップチップ実装方法 |
US6039236A (en) * | 1997-06-11 | 2000-03-21 | Soltec B.V. | Reflow soldering apparatus with improved cooling |
JPH11195870A (ja) * | 1998-01-06 | 1999-07-21 | Hitachi Ltd | 集積回路アセンブリの製造方法および接合装置 |
JP3414263B2 (ja) | 1998-06-04 | 2003-06-09 | 株式会社日立製作所 | 電子回路基板の製造方法 |
US6672500B2 (en) * | 1998-06-25 | 2004-01-06 | International Business Machines Corporation | Method for producing a reliable solder joint interconnection |
JP4503740B2 (ja) | 1999-10-14 | 2010-07-14 | オリンパス株式会社 | 撮像装置 |
US6805974B2 (en) * | 2002-02-15 | 2004-10-19 | International Business Machines Corporation | Lead-free tin-silver-copper alloy solder composition |
JPWO2004047167A1 (ja) | 2002-11-21 | 2006-03-23 | 日本電気株式会社 | 半導体装置、配線基板および配線基板製造方法 |
JP3971995B2 (ja) | 2002-12-25 | 2007-09-05 | 日本電気株式会社 | 電子部品装置 |
JP2004273654A (ja) * | 2003-03-07 | 2004-09-30 | Kumamoto Technology & Industry Foundation | 実装部品を表面実装する方法、および実装品を修理する方法 |
JP2004281491A (ja) * | 2003-03-13 | 2004-10-07 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2005005494A (ja) * | 2003-06-12 | 2005-01-06 | Sony Corp | チップ部品の実装方法及び実装基板 |
US6991967B2 (en) * | 2004-02-23 | 2006-01-31 | Asm Assembly Automation Ltd. | Apparatus and method for die attachment |
JP4525285B2 (ja) * | 2004-10-12 | 2010-08-18 | 富士通株式会社 | 電子部品及びその製造方法 |
JP4396533B2 (ja) * | 2005-01-24 | 2010-01-13 | パナソニック株式会社 | 実装体の製造方法 |
-
2006
- 2006-08-18 JP JP2006223280A patent/JP4946262B2/ja not_active Expired - Fee Related
-
2007
- 2007-01-16 TW TW096101591A patent/TWI331385B/zh not_active IP Right Cessation
- 2007-01-17 US US11/653,954 patent/US7879713B2/en not_active Expired - Fee Related
- 2007-02-07 KR KR1020070012548A patent/KR100893559B1/ko not_active IP Right Cessation
- 2007-02-09 CN CN200910141837.7A patent/CN101562142B/zh not_active Expired - Fee Related
- 2007-02-09 CN CN200710008067XA patent/CN101127314B/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2008047764A (ja) | 2008-02-28 |
CN101562142A (zh) | 2009-10-21 |
KR100893559B1 (ko) | 2009-04-17 |
US20080124834A1 (en) | 2008-05-29 |
CN101127314B (zh) | 2012-08-15 |
US7879713B2 (en) | 2011-02-01 |
CN101127314A (zh) | 2008-02-20 |
KR20080016417A (ko) | 2008-02-21 |
JP4946262B2 (ja) | 2012-06-06 |
TW200812032A (en) | 2008-03-01 |
CN101562142B (zh) | 2014-04-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20190131261A1 (en) | Package on package structure and method for forming the same | |
US7202569B2 (en) | Semiconductor device and manufacturing method of the same | |
US9230935B2 (en) | Package on package structure and method of manufacturing the same | |
KR101607790B1 (ko) | 반도체 장치 제조 방법 및 반도체 장치 | |
CN101755334B (zh) | 半导体器件 | |
TWI237310B (en) | Semiconductor device and manufacturing method of the same | |
US20040232562A1 (en) | System and method for increasing bump pad height | |
TWI331385B (en) | Mounting method of semiconductor element and manufacturing method of semiconductor device | |
JP5035134B2 (ja) | 電子部品実装装置及びその製造方法 | |
TWI502666B (zh) | Electronic parts mounting body, electronic parts, substrate | |
US20080251916A1 (en) | UBM structure for strengthening solder bumps | |
JP2008252053A (ja) | 半導体装置の製造方法及び半導体装置 | |
KR101926713B1 (ko) | 반도체 패키지 및 그 제조방법 | |
JP5333572B2 (ja) | 半導体素子の実装方法及び半導体装置の製造方法 | |
US8501545B2 (en) | Reduction of mechanical stress in metal stacks of sophisticated semiconductor devices during die-substrate soldering by an enhanced cool down regime | |
US7901997B2 (en) | Method of manufacturing semiconductor device | |
US20200152587A1 (en) | Package on package structure and method for forming the same | |
JP2001185642A (ja) | 半導体実装用パッケージ基板 | |
TW201230270A (en) | Semiconductor device and method of forming narrow interconnect sites on substrate with elongated mask openings |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |