CN110620085A - 层叠封装接合结构及其形成方法 - Google Patents

层叠封装接合结构及其形成方法 Download PDF

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Publication number
CN110620085A
CN110620085A CN201910831627.4A CN201910831627A CN110620085A CN 110620085 A CN110620085 A CN 110620085A CN 201910831627 A CN201910831627 A CN 201910831627A CN 110620085 A CN110620085 A CN 110620085A
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China
Prior art keywords
package
molding compound
layer
solder paste
die
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CN201910831627.4A
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Inventor
黄贵伟
陈威宇
陈孟泽
林威宏
郑明达
刘重希
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN110620085A publication Critical patent/CN110620085A/zh
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Abstract

本发明公开的一种形成管芯封装件和层叠封装(PoP)结构的原理的描述性实施例包括：在管芯封装件的外部连接件的金属球上方形成焊膏层。焊膏层保护金属球不被氧化。此外，所述焊膏层能够与另一个管芯封装件进行焊料与焊料之间的接合。进一步地，焊膏层移动形成在焊膏层和金属球之间且位于管芯封装件的模塑料的表面下方的的金属间化合物(IMC)层。具有位于表面下方的IMC层增强了两个管芯封装件之间的接合结构。本发明还公开了一种层叠封装接合结构及其形成方法。

Description

层叠封装接合结构及其形成方法
本申请是分案申请，其母案申请的申请号为201310384819.8、申请日为2013年08月29日、发明名称为“层叠封装接合结构及其形成方法”。
相关申请的交叉引用
本申请要求2012年12月28日提交的美国临时专利申请第61/747,130号的优先权，其全部内容结合于此作为参考。本申请也与下述共同未决和共同受让的美国专利申请相关：2012年6月18日提交的、名称为“Package on Package Structure and Method forForming the Same”的美国专利申请第13/526,073号(代理卷号：TSM12-0174)，其全部内容结合于此作为参考。
技术领域
本发明涉及半导体技术领域，更具体地，涉及层叠封装接合结构及其形成方法。
背景技术
半导体器件使用于诸如个人电脑、手机、数码相机和其他电子设备的各种电子应用中。通常制造半导体器件的步骤包括依次地在半导体衬底上方沉积绝缘层或介电层、导电层和半导体材料层，并使用光刻来图案化各种材料层以在其上形成电路部件及元件。
通过不断减小最小部件尺寸使半导体工业不断提高各种电子部件(如晶体管、二极管、电阻器、电容器等)的集成度，这使得更多的部件集成到给定区域内。在一些应用中，与过去的封装件相比，这些较小的电子部件也需要利用更小区域和/或更低高度的更小封装件。
因此，已经开始开发诸如层叠封装件(PoP)的新型封装技术，其中，具有器件管芯的顶部封装件接合至具有另一个器件管芯的底部封装件。通过采用新型封装技术，可以增加封装件的集成度。这些用于半导体的相对新型的封装技术面临着制造的挑战。
发明内容
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种管芯封装件，包括：
半导体管芯，通过模塑料围绕所述半导体管芯的至少一部分；
衬底，具有互连结构，所述半导体管芯接合至所述衬底且电连接至所述互连结构；
其中，所述模塑料覆盖所述衬底的表面的第一部分，所述半导体管芯接合至所述表面的第二部分；以及
外部连接件，围绕所述半导体管芯，所述外部连接件电连接至所述互连结构和所述半导体管芯，所述外部连接件嵌入在所述模塑料中，其中，所述外部连接件包括：
接触焊盘；
金属球，所述金属球接合至所述接触焊盘；以及
焊膏层，形成在所述金属球的一部分上方，所述焊膏层的一部分被露出。
在可选实施例中，所述焊膏层的厚度在约10μm至约50μm的范围内。
在可选实施例中，所述金属球的顶面位于所述模塑料的表面下方，且与所述模塑料的表面相距约50μm至约200μm范围内的距离。
在可选实施例中，所述焊膏层的顶面至所述模塑料的表面的距离在约5μm至约40μm的范围内。
在可选实施例中，所述金属球的直径在约100μm至约250μm的范围内。
在可选实施例中，所述互连结构使所述半导体管芯能够扇出。
在可选实施例中，第一金属间化合物(IMC)层形成在所述金属球和所述焊膏层之间，其中，所述IMC层位于所述模塑料的表面的下方。
在可选实施例中，所述第一IMC层的厚度在约3μm至约8μm的范围内。
在可选实施例中，第二金属间化合物(IMC)层形成在所述金属球和所述接触焊盘之间，其中，所述第二IMC层的厚度在约2μm至约5μm的范围内。
在可选实施例中，所述接触焊盘在接触所述金属球的表面上包括焊料。
在可选实施例中，所述金属球由铜或铜合金制成。
根据本发明的另一个方面，还提供了一种层叠封装(PoP)结构，包括：
第一管芯封装件，具有围绕第一半导体管芯的第一外部连接件，所述外部连接件通过衬底中的互连结构电连接至所述第一半导体管芯，所述外部连接件和所述第一半导体管芯均设置在所述衬底上方并嵌入在模塑料中，并且所述第一外部连接件包括：
接触焊盘；
金属球，所述金属球接合至所述接触焊盘；和
焊膏层，形成在所述金属球的一部分上方，所述焊膏层的第一部分被露出，并且所述焊膏层的第二部分位于所述模塑料的最近表面下方；以及
第二管芯封装件，具有第二外部连接件，所述第二外部连接件在一端处具有焊料层，并且所述第二外部连接件的所述焊料层接合至所述第一外部连接件的所述焊膏层。
在可选实施例中，通过所述第二管芯封装件的所述第二外部连接件的所述焊料层以及所述第一管芯封装件的所述第一外部连接件的所述焊膏层形成接合的焊料层。
在可选实施例中，所述接合的焊料层的一部分位于所述模塑料的所述最近表面的下方。
在可选实施例中，所述接合的焊料层的厚度在约10μm至约50μm的范围内。
在可选实施例中，所述金属球的顶面位于所述模塑料的表面下方，且与所述模塑料的表面相距约50μm至约200μm的范围内的距离。
在可选实施例中，第一金属间化合物(IMC)层形成在所述金属球和所述焊膏层之间，所述IMC层位于所述模塑料的表面的下方。
在可选实施例中，所述第一IMC层的厚度在约3μm至约8μm的范围内。
在可选实施例中，第二金属间化合物(IMC)层形成在所述金属球和所述接触焊盘之间，所述第二IMC层的厚度在约2μm至约5μm的范围内。
根据本发明的又一方面，还提供了一种形成管芯封装件的方法，包括：
在衬底上方形成接触焊盘，其中，所述衬底包括互连结构；
将金属球接合至所述接触焊盘；
在所述金属球的顶端上方施加焊膏层，其中，所述顶端是所述金属球相对所述衬底的最远端，所述接触焊盘、所述金属球和所述焊膏层形成连接结构；
将半导体管芯接合至所述衬底；以及
形成模塑料以填充所述半导体管芯和所述连接结构之间的空间，其中，所述焊膏层的一部分位于所述模塑料的最近表面的上方，而所述焊膏层的另一部分位于所述模塑料的所述最近表面的下方。
附图说明
为了更全面地理解本发明及其优势，现将结合附图所进行的以下描述作为参考，其中：
图1示出了根据一些实施例的封装组件的透视图；
图2A至图2I是根据一些实施例的处于不同制造阶段的层叠封装(PoP)结构的截面图；
图3示出了根据一些实施例的接合至具有底部填充物的衬底的半导体管芯；
图4A是根据一些实施例的图2E的放大区域的截面图；
图4B是根据一些实施例的图2G的放大区域的截面图；以及
图5示出了根据一些实施例的连接至具有底部填充物的管芯封装件的半导体管芯。
除非另有说明，否则不同附图中的相应数字和符号通常表示相应的部分。绘制附图以便清楚地示出实施例的相关方面且无需按比例绘制。
具体实施方式
下面，详细讨论了本发明的各个实施例的制造和使用。然而，应该理解，本发明提供了许多可以体现在各种具体环境中的可应用的概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式，且不用于限制本发明的范围。
图1示出了根据一些实施例的封装组件100的透视图，封装组件100具有管芯封装件110接合至另一管芯封装件120，另一管芯封装件120进一步结合至衬底130。诸如管芯封装件110或管芯封装件120的每一个管芯封装件至少包括半导体管芯(未示出)。每个半导体管芯包括在半导体集成电路制造中使用的衬底，并且集成电路可以形成在其中和/或其上。将半导体衬底限定为包括半导体材料的任何结构，包括但不限于块状硅、半导体晶圆、绝缘体上硅(SOI)衬底、或硅锗衬底。还可以使用包括III族元素、IV族元素、和V族元素的其他半导体材料。衬底130可以进一步包括诸如浅沟槽隔离(STI)部件或硅的局部氧化(LOCOS)部件的多个隔离部件(未示出)。隔离部件可以限定和隔离各种微电子元件。可以形成在衬底130中的各种微电子元件的实例包括晶体管(例如，金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极结型晶体管(BJT)、高压晶体管、高频晶体管、p沟道和/或n沟道场效应晶体管(PFET/NFET)等)；电阻器；二极管；电容器；电感器；熔丝；和其他合适的元件。实施各种工艺以形成各种微电子元件，该工艺包括沉积、蚀刻、注入、光刻、退火和其他合适的工艺。微电子元件互连以形成诸如逻辑器件、存储器件(例如，SRAM)、RF器件、输入/输出(I/O)器件、片上系统(SoC)器件、它们的组合以及其他合适类型的器件的集成电路器件。
可以由半导体晶圆或晶圆的一部分制成衬底130。在一些实施例中，衬底130包括硅、砷化镓、绝缘体上硅(“SOI”)或其他类似的材料。在一些实施例中，衬底130也包括诸如电阻器、电容器、电感器等的无源器件，或诸如晶体管的有源器件。在一些实施例中，衬底130包括额外的集成电路。衬底130可以进一步包括衬底通孔(TSV)且可以是中介板。此外，可以由其他材料制成衬底130。例如，在一些实施例中，衬底130是多层电路板。在一些实施例中，衬底130也包括双马来酰亚胺三嗪(BT)树脂。FR-4(由编织的玻璃纤维布与耐火的环氧树脂粘合剂组成的复合材料)、陶瓷、玻璃、塑料、胶带、薄膜、或可以带有需要接收导电端子的导电焊盘或接合焊盘的其他支撑材料。
图1示出了根据一些实施例的管芯封装件110通过接合结构115接合至另一管芯封装件120以及管芯封装件120也通过接合结构125接合至衬底130从而形成封装组件100。接合结构115和/或125的结构和形成工艺影响封装组件100的产率和可靠性。
图2A至图2I是根据一些实施例的管芯封装件110位于管芯封装件120上方的层叠封装(PoP)结构处于不同制造阶段的截面图。图2A示出了根据一些实施例的具有用于制造外部连接件的接触焊盘210的衬底200。可以由半导体晶圆或晶圆的一部分制成衬底200。在一些实施例中，衬底200包括硅、砷化镓、绝缘体上硅(“SOI”)或其他相似的材料。在一些实施例中，衬底200也包括诸如电阻器、电容器、电感器等的无源器件，或诸如晶体管的有源器件。在一些实施例中，衬底200包括额外的集成电路。衬底200可以进一步包括衬底通孔(TSV)且可以是中介板。此外，可以由其他材料制成衬底200。例如，在一些实施例中，衬底200是多层电路板。在一些实施例中，衬底200也包括双马来酰亚胺三嗪(BT)树脂、FR-4、FR-5(与FR-4类似)、陶瓷、玻璃、塑料、胶带、薄膜或可以带有需要接收导电端子的导电焊盘或接合焊盘的其他支撑材料。可以由导电材料制成接触焊盘210，且接触焊盘210连接至衬底200中的互连件(未示出)。
然后，根据一些实施例，如图2B所示，金属球240安装到接触焊盘210上并且与接触焊盘210接合。安装工艺可以包括将金属球240放置在接触焊盘210上，并实施回流工艺以将金属球240接合至接触焊盘210。在一些实施例中，回流温度在约180℃至约260℃的范围内。在一些实施例中，由暴露于空气中时易于氧化的的导电材料(诸如铜或铜合金)制成金属球240。
当铜在暴露于空气中时易于氧化。表面氧化层增加电阻并降低管芯封装件之间(诸如管芯封装件110和管芯封装件120之间)的接合结构的接合质量。如图2C所示，根据一些实施例，为防止金属球240发生表面氧化，将焊膏层241施加到金属球240的远离接触焊盘210的表面上。焊膏层241也可以与管芯封装件120的外部连接件上的焊料接合。根据一些实施例，通过焊料印刷工艺使用焊料印刷装置形成焊膏层241。
随后，根据一些实施例，如图2D所示，半导体管芯105放置在衬底200上。每一个半导体管芯105放置在接合的金属球240之间。在一些实施例中，实施回流工艺以将半导体管芯105上的连接件(未示出)接合至衬底200上的接触焊盘(未示出)，从而形成接合结构153。接合结构153与衬底200的表面上的接触结构(未示出)连接。由于回流的温度接近或超过焊料的溶化温度，所以回流工艺改变了金属球240上焊膏层241的轮廓。如图2D所示，焊膏层241进一步在金属球240的顶面上展开(或“湿润”)。接触焊盘210、接合的金属球240和焊膏层241形成外部连接件255。
在一些实施例中，如图3所示，使用底部填充物154填充半导体管芯105和衬底200之间的空间。底部填充物154支撑半导体管芯105，并防止使半导体管芯105和衬底200中的导电元件(互连件)电连接的接合结构153上的焊料接点(未示出)发生断裂。
然而，在半导体管芯105接合至衬底200后形成底部填充物154是可选的。在一些实施例中，并未形成底部填充物154。根据一些实施例，可以由热固性聚合物制成底部填充物154。例如，底部填充物154可以由环氧树脂(胺类、苯酚类、酸酐类等)、硅填充物、固化剂、添加剂和/或硬化剂制成或者底部填充物154包括上述这些物质。
在接合半导体管芯105或可选地形成底部填充物154之后，在衬底200的表面上形成模塑料260以填充外部连接件255和半导体管芯105之间的空间。如果未形成填充半导体管芯105和衬底200之间的空间的底部填充物154，则将模塑的底部填充物(MUF)用作模塑料260以达到底部填充的目的。这种实施方式通过消除底部填充物154的形成步骤从而节省了工艺成本。图2E示出了根据一些实施例的模塑料填充外部连接件255和半导体管芯105之间的空间，以及填充半导体管芯105下面的空间。在一些实施例中，模塑料260具有填充物。模塑料260支撑管芯封装件110并防止接合结构153上的焊料接点以及金属球240和接触焊盘210之间的焊料接点发生断裂。此外，由于在热循环后衬底200上材料的热膨胀系数(CTE)失配，模塑料260也可以防止衬底200上层叠封装结构的弯曲(变形)。在一些实施例中，由环氧树脂(胺类、苯酚类、酸酐类等)、硅填充物、固化剂、添加剂和/或硬化剂材料制成模塑料260。
图4A是根据一些实施例的图2E的放大区域250的截面图。图4A示出了根据一些实施例的包括衬底200及外部连接件(安装的金属球结构)255的区域250。衬底200包括互连结构205，互连结构205包括金属线204和通孔206的一层或多层。互连结构205连接至接触焊盘210和位于衬底200的相对侧上的接触焊盘207，其中，接触焊盘210接合至金属球240。互连结构205也与半导体管芯105的接合结构253连接以使半导体管芯105能够扇出。在一些实施例中，接触焊盘210和207包括铝、铜、银、金、镍、钨、它们的合金和/或它们的多层。在一些实施例中，由焊锡料制成接触焊盘210。在一些实施例中，由铜或铜合金制成接触焊盘207。
图4A示出了位于模塑料260的顶面261下方的焊膏层241的一部分。在一些实施例中，在焊膏层241和金属球240之间形成金属间化合物(IMC)层242。在一些实施例中，焊膏层241的厚度D1在约10μm至约50μm的范围内。在一些实施例中，IMC层242的厚度在约2μm至约5μm的范围内。在一些实施例中，IMC层243形成在接触焊盘210和金属球240之间。在一些实施例中，IMC层243的厚度在约3μm至约8μm的范围内。在一些实施例中，金属球240与IMC层242均嵌入在模塑料260内。在一些实施例中，金属球240的顶部至模塑料260的表面261的距离D2在约50μm至约200μm的范围内。
在一些实施例中，焊膏层241的顶部至模塑料260的表面261的距离D4在约5μm至约40μm的范围内。与IMC层水平于或高于表面261相比，IMC层242低于表面261使得外部连接件255和管芯封装件110的连接件之间的接合结构更强健。
图4A示出了接触焊盘210的焊料的一部分覆盖金属球240较低部分表面，其可以称为焊料润湿。焊料润湿可以发生在将金属球240安装到接触焊盘210上的回流工艺期间和/或在将半导体管芯105接合至衬底210期间(或接合结构153的形成期间)。在一些实施例中，金属球240的(最大)宽度W1在约100μm到约200μm的范围内。在一些实施例中，金属球240之间的节距(Pitch)P1在约150μm至约250μm的范围内。
在一些实施例中，在接触焊盘210上方形成接合层(未示出)以助于金属球240与接触焊盘210接合。例如，如果导电焊盘210由铜制成，则接合层可以使用可用于使铜与铜接合的焊料制成。在一些实施例中，接合层由焊料或诸如Sn-Ag、Sn-Ag-Cu、Sn-Bi、Sn-Cu等的焊料合金制成。在一些实施例中，接合层由包括Sn、Pb、Ag、Cu、Ni、铋(Bi)或它们的组合的焊料合金制成。也可以在接触焊盘207上方形成与上文所述的相似的接合层。在一些实施例中，接合层的厚度在约0.5μm至约10μm的范围内。
如上文所述，互连结构205包括金属线204和通孔206的一层或多层。根据一些实施例，金属线204和通孔206由铜或铜合金形成。互连结构205被层间电介质(ILD)(或金属间电介质，IMD)围绕且隔离，其中层间电介质(ILD)(或金属间电介质，IMD)可以由非掺杂的硅玻璃、掺杂的膜、低介电常数(低k)电介质、聚合物、具有填充物的聚合物或它们的组合制成。电介质聚合物可以包括诸如聚酰亚胺、聚苯并恶唑(PBO)或苯并环丁烯(BCB)的材料。可以将诸如石英纤维的填充物添加到聚合物中以增加聚合物的强度。ILD可以包括一层或多层。在一些实施例中，一个或多个钝化层围绕接触焊盘210。由诸如聚酰亚胺、PBO或BCB的聚合物制成一个或多个钝化层，钝化层吸收在接合工艺期间施加于接触焊盘210和衬底200上的应力。类似地，一个或多个钝化层也可以围绕接触焊盘207以达到上述目的。如图2F所示，根据一些实施例，在形成模塑料260后，连接件270接合至位于衬底200的另一侧(与封装件110相对的一侧)上的接触焊盘(207)。连接件270由导电材料制成。这类导电材料可以是焊料、焊料合金、铜、铜合金、金或金合金等。如上文所述，可以具有覆盖导电焊盘(207)的接合层(未示出)。通过回流工艺将连接件270接合至导电焊盘207。在一些实施例中，连接件270为球栅阵列(BGA)球。可以在形成模塑料260之后或在附接连接件270之后形成管芯封装件120。
根据一些实施例，如图2G所示，在形成连接件270后，管芯封装件110接合至管芯封装件120。然后，如图2G所示，根据一些实施例，将封装件110放置在衬底200上方并安装在金属球240上。根据一些实施例，每一个封装件110都包括两个半导体管芯112和113，其中管芯113设置在管芯112上方。然而，封装件110也可以包括一个半导体管芯或两个以上半导体管芯。在一些实施例中，具有位于管芯112和113之间的粘合层121。半导体管芯112和113可以包括如上文所述的半导体管芯105的多种微电子元件。已在上文中描述这些多种微电子元件的实例。半导体管芯112接合至衬底115。衬底115可以包括上文所述的用于半导体管芯105的衬底的多种材料和/或组分。根据一些实施例，半导体管芯112通过接合引线114电连接至衬底115中的导电元件(未示出)。相似地，半导体管芯113通过接合引线116电连接至衬底115中的导电元件。封装件110还包括覆盖半导体管芯112和113的模塑料111，以及接合引线114和116。
根据一些实施例，每一个封装件110包括多个连接件117，并在接合、围绕半导体管芯105后成为117’。在一些实施例中，由诸如焊料、焊料合金等的导电材料制成连接件117。在衬底115的表面上的接触焊盘118上形成连接件117以电连接至衬底115中的元件。根据一些实施例，在封装件110放置在衬底200上方且封装件110的连接件117与金属球240上方的焊膏层241接触后，实施回流工艺以将连接件117接合至焊膏层241(其接合至金属球240)，从而形成焊料层117’。如图4B所示，根据一些实施例中，如果连接件117由焊料制成或在与焊膏层241相接触的端部具有焊料层，则在回流工艺下将两个焊料层合并成一层以形成强健的接合结构265。
图4B示出了根据一些实施例的在管芯封装件110接合至封装件120后的区域250。图4B示出了接合结构265包括接触焊盘118和接合的焊料层117’，其中焊料层117’通过连接件117和焊膏层241结合而形成。接合结构265还包括金属球240和接触焊盘210。如图4B所示，根据一些实施例，具有位于焊料层117’和金属球240之间的IMC层242’，以及位于金属球240和接触焊盘210之间的IMC层243’。与焊料与铜之间的接合，或焊料与氧化铜之间的接合相比，接合的焊料层117’的焊料和焊料之间的接合更强健。此外，接合结构265不具有界面氧化铜层。此外，接合的焊料层117’和IMC层242’延伸在模塑料260的表面261下方，而不是位于与表面261平齐的表面处或高于表面261的表面。因此，接合结构265比接合界面接近或高于表面261的接合结构更强健。在一些实施例中，焊料的总高度D3在约80μm至约130μm的范围内。在一些实施例中，模塑料260的表面261与封装件110(或衬底115)的底面101之间的高度H1在30μm至约80μm的范围内。
在一些实施例中，由于额外的热循环形成了接合结构265，因此IMC层242’比图4A的IMC层242更厚。在一些实施例中，IMC层242’的厚度在约2μm至约5μm的范围内。在一些实施例中，IMC层243’的厚度在约3μm至约8μm的范围内。
根据一些实施例，如图2H所示，在管芯封装件110接合至管芯封装件120后，形成模塑料267以覆盖管芯封装件110下方或管芯封装件110之间的空间。上文中已经描述了模塑料267的材料及形成方法。模塑料267保护接合结构265。如上文提到的，模塑料267由模塑的底部填充(MUF)材料制成并填充封装件110下方(或封装件110和120之间)的空间。根据一些实施例，如图5所示，形成底部填充物268以填充封装件110和120之间的空间。底部填充物268保护接合结构265。图5示出了围绕管芯105形成的底部填充物154和模塑料260。
如上文所述，可以形成模塑料267或底部填充物268以保护接合结构265。在一些实施例中，未形成保护接合结构265的模塑料或底部填充物。然后，诸如图2G、图2H或图5的结构的层叠封装(PoP)结构经历锯切工艺以将PoP结构分割为单个的PoP器件。图2I示出了根据一些实施例的在锯切(或分割)工艺后的PoP器件(或结构)150。图2I示出了管芯封装件110具有底部填充物268。如上文所述，管芯封装件110可以被诸如图2H的模塑料267的模塑料覆盖或不被任一个覆盖。
形成管芯封装件和层叠封装(PoP)结构的原理的描述性实施例包括：在管芯封装件的外部连接件的金属球上方形成焊膏层。焊膏层保护金属球不被氧化。此外，焊膏层能够与另一个管芯封装件进行焊料与焊料之间的接合。此外，焊膏层使形成在焊膏层和金属球之间且位于管芯封装件的模塑料表面下方的金属间化合物(IMC)层移动。具有位于所述表面下方的IMC层加强了两个管芯封装件之间的接合结构。
在一些实施例中，提供了管芯封装件。管芯封装件包括半导体管芯，以及被模塑料围绕的半导体管芯的至少一部分。管芯封装件还包括具有互连结构的衬底，半导体管芯接合至衬底并且电连接至互连结构。管芯封装件进一步包括围绕半导体管芯的模塑料，并且模塑料覆盖衬底表面的第一部分。半导体管芯接合至表面的第二部分。此外，管芯封装件包括围绕半导体管芯的外部连接件，并且外部连接件电连接至互连结构和半导体管芯。外部连接件嵌入在模塑料中。外部连接件包括接触焊盘以及金属球。金属球接合至接触焊盘。外部连接件还包括形成在金属球的一部分上方的焊膏层，并且焊膏层的一部分被暴露。
在其他一些实施例中，提供了层叠封装(PoP)结构。PoP结构包括第一管芯封装件，具有围绕第一半导体管芯的第一外部连接件，并且外部连接件通过衬底中的互连结构电连接至第一半导体管芯。外部连接件和第一半导体管芯均设置在衬底上方且嵌入在模塑料中。第一外部连接件包括接触焊盘和金属球。金属球接合至接触焊盘。第一外部连接件还包括形成在金属球的一部分上方的焊膏层。焊膏层的第一部分被露出，且焊膏层的第二部分位于模塑料的最近表面下方。PoP结构还包括具有第二外部连接件的第二管芯封装件，并且第二外部连接件在一个端部具有焊料层。第二外部连接件的焊料层接合至第一外部连接件的焊膏层。
在又一些实施例中，提供了一种形成管芯封装件的方法。该方法包括在衬底上方形成接触焊盘，并且衬底包括互连结构。所述方法还包括将金属球接合至接触焊盘，并且在金属球的顶端上方施加焊膏层。顶端是金属球相对于衬底的最远端，并且接触焊盘、金属球和焊膏层形成连接结构。该方法进一步包括将半导体管芯接合至衬底，并且形成模塑料以填充半导体管芯和连接结构之间的空间。焊膏层的一部分位于模塑料的最近表面的上方而焊膏层的其他部分则位于模塑料的最近表面的下方。
尽管已经详细地描述了本发明的实施例及其优势，但应该理解，在不背离所附权利要求限定的本发明的精神和范围的情况下，可以对本文做各种不同的改变、替代和更改。例如，本领域普通技术人员将容易地理解本文中所描述的多种部件、功能、工艺和材料可以在本发明的范围内进行改变。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、物质组成、工具、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明的实施例，可以利用现有的或今后将被开发的、与本发明的所述相应实施例执行基本相同的功能或实现基本相同结果的工艺、机器、制造、物质组成、工具、方法或步骤。相应地，附加的权利要求旨在将这些工艺、机器、制造、物质组成、工具、方法或步骤包括在它们的范围内。

Claims (20)

1.一种管芯封装件，包括：
半导体管芯，通过模塑料围绕所述半导体管芯的至少一部分；
衬底，具有互连结构，所述半导体管芯接合至所述衬底且电连接至所述互连结构；
其中，所述模塑料覆盖所述衬底的表面的第一部分，所述半导体管芯接合至所述表面的第二部分；以及
外部连接件，围绕所述半导体管芯，所述外部连接件电连接至所述互连结构和所述半导体管芯，所述外部连接件嵌入在所述模塑料中，其中，所述外部连接件包括：
接触焊盘；
金属球，所述金属球接合至所述接触焊盘，其中，所述金属球包括与所述接触焊盘接触的底面、与所述模塑料接触的侧面以及位于所述模塑料中的顶面；以及
焊膏层，形成在所述金属球的顶面上方，所述焊膏层包括与所述金属球的顶面接触的底面、与所述模塑料接触并位于其中的第一顶面部分、以及由所述模塑料露出的第二顶面部分，其中所述焊膏层的底面、所述第一顶面部分和所述第二顶面部分向远离所述金属球的方向突出。
2.根据权利要求1所述的管芯封装件，其中，所述焊膏层的厚度在10μm至50μm的范围内。
3.根据权利要求1所述的管芯封装件，其中，所述金属球的顶面位于所述模塑料的表面下方，且与所述模塑料的表面相距50μm至200μm范围内的距离。
4.根据权利要求1所述的管芯封装件，其中，所述焊膏层的顶面至所述模塑料的表面的距离在5μm至40μm的范围内。
5.根据权利要求1所述的管芯封装件，其中，所述金属球的直径在100μm至250μm的范围内。
6.根据权利要求1所述的管芯封装件，其中，所述互连结构使所述半导体管芯能够扇出。
7.根据权利要求1所述的管芯封装件，其中，第一金属间化合物层形成在所述金属球和所述焊膏层之间，其中，所述第一金属间化合物层位于所述模塑料的表面的下方。
8.根据权利要求7所述的管芯封装件，其中，所述第一金属间化合物层的厚度在3μm至8μm的范围内。
9.根据权利要求1所述的管芯封装件，其中，第二金属间化合物层形成在所述金属球和所述接触焊盘之间，其中，所述第二金属间化合物层的厚度在2μm至5μm的范围内。
10.根据权利要求1所述的管芯封装件，其中，所述接触焊盘在接触所述金属球的表面上包括焊料。
11.根据权利要求1所述的管芯封装件，其中，所述金属球由铜或铜合金制成。
12.一种层叠封装结构，包括：
第一管芯封装件，具有围绕第一半导体管芯的第一外部连接件，所述外部连接件通过衬底中的互连结构电连接至所述第一半导体管芯，所述外部连接件和所述第一半导体管芯均设置在所述衬底上方并嵌入在模塑料中，并且所述第一外部连接件包括：
接触焊盘；
金属球，所述金属球接合至所述接触焊盘，其中，所述金属球包括与所述接触焊盘接触的底面、与所述模塑料接触的侧面以及位于所述模塑料中的顶面；和
焊膏层，形成在所述金属球的顶面上方，所述焊膏层包括与所述金属球的顶面接触的底面、与所述模塑料接触并位于其中的第一顶面部分、以及由所述模塑料露出的第二顶面部分，其中所述焊膏层的底面、所述第一顶面部分和所述第二顶面部分向远离所述金属球的方向突出；以及
第二管芯封装件，具有第二外部连接件，所述第二外部连接件在一端处具有焊料层，并且所述第二外部连接件的所述焊料层接合至所述第一外部连接件的所述焊膏层。
13.根据权利要求12所述的层叠封装结构，其中，通过所述第二管芯封装件的所述第二外部连接件的所述焊料层以及所述第一管芯封装件的所述第一外部连接件的所述焊膏层形成接合的焊料层。
14.根据权利要求13所述的层叠封装结构，其中，所述接合的焊料层的一部分位于所述模塑料的所述最近表面的下方。
15.根据权利要求14所述的层叠封装结构，其中，所述接合的焊料层的厚度在10μm至50μm的范围内。
16.根据权利要求12所述的层叠封装结构，其中，所述金属球的顶面位于所述模塑料的表面下方，且与所述模塑料的表面相距50μm至200μm的范围内的距离。
17.根据权利要求12所述的层叠封装结构，其中，第一金属间化合物层形成在所述金属球和所述焊膏层之间，所述第一金属间化合物层位于所述模塑料的表面的下方。
18.根据权利要求17所述的层叠封装结构，其中，所述第一金属间化合物层的厚度在3μm至8μm的范围内。
19.根据权利要求12所述的层叠封装结构，其中，第二金属间化合物层形成在所述金属球和所述接触焊盘之间，所述第二金属间化合物层的厚度在2μm至5μm的范围内。
20.一种形成管芯封装件的方法，包括：
在衬底上方形成接触焊盘，其中，所述衬底包括互连结构；
将金属球接合至所述接触焊盘；
在所述金属球的顶端上方施加焊膏层，其中，所述顶端是所述金属球相对所述衬底的最远端，所述接触焊盘、所述金属球和所述焊膏层形成连接结构；
将半导体管芯接合至所述衬底；以及
形成模塑料以填充所述半导体管芯和所述连接结构之间的空间，其中，所述焊膏层的一部分位于所述模塑料的最近表面的上方，而所述焊膏层的另一部分位于所述模塑料的所述最近表面的下方，
其中，所述金属球包括与所述接触焊盘接触的底面、与所述模塑料接触的侧面以及位于所述模塑料中的顶面，所述焊膏层包括与所述金属球的顶面接触的底面、与所述模塑料接触并位于其中的第一顶面部分、以及由所述模塑料露出的第二顶面部分，其中所述焊膏层的底面、所述第一顶面部分和所述第二顶面部分向远离所述金属球的方向突出。
CN201910831627.4A 2012-12-28 2013-08-29 层叠封装接合结构及其形成方法 Pending CN110620085A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024125547A1 (zh) * 2022-12-16 2024-06-20 维沃移动通信有限公司 封装结构、电子设备和封装方法

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9768137B2 (en) * 2012-04-30 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Stud bump structure for semiconductor package assemblies
US9111930B2 (en) * 2013-03-12 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package on-package with cavity in interposer
CN105705336B (zh) * 2013-10-28 2018-04-24 惠普发展公司，有限责任合伙企业 以低轮廓封装体封装键合线的方法
TWI550791B (zh) * 2014-01-16 2016-09-21 矽品精密工業股份有限公司 半導體封裝件及其製法
US9711485B1 (en) 2014-02-04 2017-07-18 Amkor Technology, Inc. Thin bonded interposer package
CN104659004A (zh) * 2014-12-30 2015-05-27 华天科技（西安）有限公司 一种PoP封装结构及其制造方法
US20160379806A1 (en) * 2015-06-25 2016-12-29 Lam Research Corporation Use of plasma-resistant atomic layer deposition coatings to extend the lifetime of polymer components in etch chambers
CN105161435A (zh) * 2015-07-06 2015-12-16 华进半导体封装先导技术研发中心有限公司 控制球高且避免掉球的PoP堆叠封装工艺
US9941260B2 (en) * 2015-09-16 2018-04-10 Mediatek Inc. Fan-out package structure having embedded package substrate
US20170287838A1 (en) 2016-04-02 2017-10-05 Intel Corporation Electrical interconnect bridge
TWI601219B (zh) * 2016-08-31 2017-10-01 矽品精密工業股份有限公司 電子封裝件及其製法
US10529697B2 (en) * 2016-09-16 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of forming the same
US10297471B2 (en) * 2016-12-15 2019-05-21 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out structure and method of fabricating the same
KR102373440B1 (ko) * 2017-03-17 2022-03-14 삼성디스플레이 주식회사 디스플레이 패널 및 이를 구비하는 디스플레이 장치
US10522505B2 (en) 2017-04-06 2019-12-31 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method for manufacturing the same
US10438930B2 (en) * 2017-06-30 2019-10-08 Intel Corporation Package on package thermal transfer systems and methods
US10204814B1 (en) * 2017-07-28 2019-02-12 Stmicroelectronics, Inc. Semiconductor package with individually molded leadframe and die coupled at solder balls
TWI667743B (zh) * 2017-10-20 2019-08-01 矽品精密工業股份有限公司 電子封裝件及其製法
KR102179165B1 (ko) 2017-11-28 2020-11-16 삼성전자주식회사 캐리어 기판 및 상기 캐리어 기판을 이용한 반도체 패키지의 제조방법
US10403594B2 (en) * 2018-01-22 2019-09-03 Toyota Motor Engineering & Manufacturing North America, Inc. Hybrid bonding materials comprising ball grid arrays and metal inverse opal bonding layers, and power electronics assemblies incorporating the same
US10515936B1 (en) 2018-06-25 2019-12-24 Powertech Technology Inc. Package structure and manufacturing method thereof
US10535644B1 (en) * 2018-06-29 2020-01-14 Taiwan Semiconductor Manufacturing Co., Ltd. Manufacturing method of package on package structure
CN113130432B (zh) 2019-12-30 2022-12-27 华为机器有限公司 一种电子模块及电子设备

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7009297B1 (en) * 2000-10-13 2006-03-07 Bridge Semiconductor Corporation Semiconductor chip assembly with embedded metal particle
CN101211901A (zh) * 2006-12-26 2008-07-02 新光电气工业株式会社 包含电子元件的基板
US20090146301A1 (en) * 2007-12-11 2009-06-11 Panasonic Corporation Semiconductor device and method of manufacturing the same
US20120319274A1 (en) * 2011-06-20 2012-12-20 Shinko Electric Industries Co., Ltd. Method of manufacturing semiconductor device, and semiconductor device

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3431406B2 (ja) 1996-07-30 2003-07-28 株式会社東芝 半導体パッケージ装置
JPH11145176A (ja) 1997-11-11 1999-05-28 Fujitsu Ltd ハンダバンプの形成方法及び予備ハンダの形成方法
US6337445B1 (en) 1998-03-16 2002-01-08 Texas Instruments Incorporated Composite connection structure and method of manufacturing
US6333563B1 (en) 2000-06-06 2001-12-25 International Business Machines Corporation Electrical interconnection package and method thereof
US6781065B1 (en) 2000-06-08 2004-08-24 The Whitaker Corporation Solder-coated articles useful for substrate attachment
US7262082B1 (en) * 2000-10-13 2007-08-28 Bridge Semiconductor Corporation Method of making a three-dimensional stacked semiconductor package with a metal pillar and a conductive interconnect in an encapsulant aperture
US20020151164A1 (en) 2001-04-12 2002-10-17 Jiang Hunt Hang Structure and method for depositing solder bumps on a wafer
TW530344B (en) 2002-05-10 2003-05-01 Walsin Advanced Electronics Conductive ball for electrical connection and applications thereof
KR20050042060A (ko) 2002-09-27 2005-05-04 가부시키가이샤 네오맥스 땜납 피복 볼 및 그 제조방법과 반도체 접속구조의 형성방법
US7345361B2 (en) * 2003-12-04 2008-03-18 Intel Corporation Stackable integrated circuit packaging
US7213329B2 (en) 2004-08-14 2007-05-08 Samsung Electronics, Co., Ltd. Method of forming a solder ball on a board and the board
JP2009141169A (ja) 2007-12-07 2009-06-25 Shinko Electric Ind Co Ltd 半導体装置
US7781232B2 (en) 2008-01-17 2010-08-24 International Business Machines Corporation Method to recover underfilled modules by selective removal of discrete components
US7989950B2 (en) 2008-08-14 2011-08-02 Stats Chippac Ltd. Integrated circuit packaging system having a cavity
JP5045688B2 (ja) 2009-01-29 2012-10-10 日立金属株式会社 半導体装置
US8163597B2 (en) 2009-03-24 2012-04-24 Stats Chippac, Ltd. Semiconductor device and method of forming no-flow underfill material around vertical interconnect structure
JP5279631B2 (ja) * 2009-06-23 2013-09-04 新光電気工業株式会社 電子部品内蔵配線基板と電子部品内蔵配線基板の製造方法
JP5214554B2 (ja) * 2009-07-30 2013-06-19 ラピスセミコンダクタ株式会社 半導体チップ内蔵パッケージ及びその製造方法、並びに、パッケージ・オン・パッケージ型半導体装置及びその製造方法
WO2011014409A1 (en) 2009-07-30 2011-02-03 Megica Corporation System-in packages
TWI474414B (zh) 2009-08-25 2015-02-21 Advanced Semiconductor Eng 可堆疊式半導體封裝結構及半導體製程
JP5481724B2 (ja) * 2009-12-24 2014-04-23 新光電気工業株式会社 半導体素子内蔵基板
US8557629B1 (en) * 2010-12-03 2013-10-15 Amkor Technology, Inc. Semiconductor device having overlapped via apertures
KR20120089150A (ko) * 2011-02-01 2012-08-09 삼성전자주식회사 패키지 온 패키지
JP2013138169A (ja) * 2011-11-29 2013-07-11 Hitachi Ltd 貼り合せ基板およびその製造方法
US9219030B2 (en) 2012-04-16 2015-12-22 Taiwan Semiconductor Manufacturing Co., Ltd. Package on package structures and methods for forming the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7009297B1 (en) * 2000-10-13 2006-03-07 Bridge Semiconductor Corporation Semiconductor chip assembly with embedded metal particle
CN101211901A (zh) * 2006-12-26 2008-07-02 新光电气工业株式会社 包含电子元件的基板
US20090146301A1 (en) * 2007-12-11 2009-06-11 Panasonic Corporation Semiconductor device and method of manufacturing the same
US20120319274A1 (en) * 2011-06-20 2012-12-20 Shinko Electric Industries Co., Ltd. Method of manufacturing semiconductor device, and semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024125547A1 (zh) * 2022-12-16 2024-06-20 维沃移动通信有限公司 封装结构、电子设备和封装方法

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