CN102439713A - 具有电隔离背表面的凸点自隔离的GaN晶体管芯片 - Google Patents

具有电隔离背表面的凸点自隔离的GaN晶体管芯片 Download PDF

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CN102439713A
CN102439713A CN2010800153609A CN201080015360A CN102439713A CN 102439713 A CN102439713 A CN 102439713A CN 2010800153609 A CN2010800153609 A CN 2010800153609A CN 201080015360 A CN201080015360 A CN 201080015360A CN 102439713 A CN102439713 A CN 102439713A
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semiconductor device
silicon substrate
active region
transistor
heat sink
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CN102439713B (zh
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亚力山大·利道
罗伯特·比奇
阿兰娜·纳卡塔
曹建军
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Abstract

一种半导体器件，包括硅衬底、复合半导体材料、在所述硅衬底和复合物半导体材料之间的绝缘材料、以及顶表面，顶表面包括电连接的装置以及钝化材料，其中该钝化材料是氮化硅、二氧化硅或两者的组合。本发明通过包括用于将器件的硅衬底电隔离的AlN籽晶层而消除了对在热沉和表面加装器件的背表面之间的厚的电绝缘体的需求。该器件的侧壁也与器件的活性区域电隔离。

Description

具有电隔离背表面的凸点自隔离的GaN晶体管芯片
背景技术
多年以来在硅中制成的器件被直接加装到印刷电路板上。问题是器件的背表面仍可为电活性的，这可导致背表面的侵蚀和温度升高。如果使用用于冷却的热沉，器件的背表面上通常需要绝缘，这增加器件尺寸和成本。
图1示出表面加装到印刷电路板17上的已知器件1的实例。印刷电路板17具有铜走线15。由聚酰亚胺钝化物16隔开的焊料凸点14将器件的活性区域13电和物理地耦联到位于印刷电路板17上的铜走线15。器件1具有侧壁12和背表面11。侧壁12和背表面11电连接到位于前侧的电路。
图2示出热沉19，其附连到器件1以便从硅衬底10的背表面11传导散热。当热沉19附连到器件1的背表面11时，在硅衬底10和热沉19之间必须加装绝缘层18以便防止热沉19通过与电连接到前侧的背表面11接触而变为电活性。但是，加装绝缘层18不利地阻止热沉19从器件1传导散热的能力。
因此，需要解决上述问题的方案，即需要这样一种器件，其中热沉可直接连接到表面加装器件的背表面，而无需阻止热量从器件通过的绝缘层。
发明内容
本发明通过在硅衬底和铝镓氮(AlGaN)缓冲层之间设置氮化铝(AlN)籽晶层以便防止硅衬底变成电活性以及通过将活性区域与器件侧壁电隔离而解决现有技术中的上述问题。
附图说明
图1示出现有技术器件的侧视图。
图2示出具有附连的热沉的图1所示现有技术器件的侧视图。
图3示出根据本发明器件的侧视图。
图4示出具有附连的热沉的本发明器件的侧视图。
具体实施方式
本发明消除了对绝缘层的需求，由此通过在硅衬底和铝镓氮缓冲层之间设置氮化铝(AlN)籽晶层以便防止硅衬底变成电活性以及通过使得器件的侧壁与活性区域电隔离而改善了热量到热沉的传导性。
图3示出了本发明的优选实施例，表面加装到印刷电路板17上的增强型GaN晶体管2。如现有技术中的那样，由聚酰亚胺钝化物16隔开的焊料凸点14将器件的活性区域13电和物理地耦联到位于印刷电路板17上的铜走线15。到活性区域13的电连接包括至少一个栅极、至少一个漏极以及至少两个源极，其中一个源极用作Kelvin连接。
本发明的器件2如下形成。低温、几乎无定形氮化铝(AlN)层沉积在硅衬底10上。然后生长更高温度的AlN层，完成AlN层21的形成。上述第二个AlN层具有许多晶体缺陷。接着，在AlN籽晶层21上方生长铝镓氮层，使得晶体变得更好。然后生长晶体结构甚至更好的未掺杂GaN层。形成二维电子气(2DEG)所必需的器件活性区域13的铝镓氮帽在周边被蚀刻掉以便防止2DEG到达器件的边缘。未掺杂的GaN层延伸到上述边缘，并且类似于下面的AlGaN缓冲层和AlN层21，未掺杂的GaN层不导电，从而使得器件的边缘为非活性的。同样，硅衬底10通过AlN籽晶层21与器件活性区域13电绝缘。作为该电隔离的结果，降低了器件2的背表面11以及侧壁12上的侵蚀和温度。
图4示出热沉19附连到器件2的背表面11以便散热。设置用于将硅衬底10电隔离的绝缘的AlN籽晶层21以及电隔离侧壁使得允许热沉19直接连接到器件2的背表面11，而无需如图2中所示的绝缘层18。因此，器件2不具有如图2中所示的器件1的问题；也就是，不存在阻止热沉19从器件传导散热的能力的厚绝缘层18。此外，器件2比器件1更耐湿。所有需要的就是在器件2的顶表面上方具有表面钝化物，优选氮化硅、二氧化硅或两者的组合。无需二次成型(overmolding)，因此提供芯片级包装的GaN功率晶体管。
通过将本发明的多个有源器件集成到硅衬底上可形成各种电路。例如，本发明的GaN晶体管可以半桥或全桥构造集成到硅衬底上。本发明的GaN功率晶体管还可由同一硅衬底上的小型激励晶体管所激励。
上述说明和附图仅仅被认为是实现本文所述特征和优势的本发明特定实例的示例性说明。可对本发明进行改变和替换。因此，不应该认为在此所述的本发明实施例受到前述说明和附图的限制。

Claims (12)

1.一种半导体器件，包括：
硅衬底；
包括活性区域的复合半导体材料；
在所述硅衬底和活性区域之间的绝缘材料；以及
顶表面，包括：
电连接到所述活性区域的装置；及
第一钝化材料，其中该钝化材料是氮化硅、二氧化硅或两者的组合。
2.根据权利要求1所述的半导体器件，其中所述复合半导体材料由包括镓、氮和铝组合物的各种层形成。
3.根据权利要求1所述的半导体器件，其中所述半导体器件是增强型晶体管。
4.根据权利要求2所述的半导体器件，其中所述半导体器件是增强型GaN晶体管。
5.根据权利要求1所述的半导体器件，还包括聚酰亚胺塑料的第二钝化材料。
6.根据权利要求1所述的半导体器件，其中所述活性区域不延伸到该半导体器件的边缘。
7.根据权利要求1所述的半导体器件，还包括直接加装到所述硅衬底的表面的热沉，无需在衬底和热沉之间的绝缘层。
8.根据权利要求1所述的半导体器件，其中所述电连接包括由铜、铅、银、锑和锡的各种组合物形成的焊料凸点。
9.根据权利要求1所述的半导体器件，其中所述电连接包括至少一个栅极、至少一个漏极、以及至少两个源极，其中一个源极用作Kelvin连接。
10.根据权利要求3所述的半导体器件，其中多个有源器件集成到该硅衬底上。
11.根据权利要求3所述的半导体器件，其中所述晶体管为半桥或全桥构造。
12.根据权利要求3所述的半导体器件，其中所述晶体管由位于同一硅衬底上的小型激励晶体管所激励。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681858A (zh) * 2012-09-19 2014-03-26 株式会社东芝 半导体装置
CN103811365A (zh) * 2014-01-23 2014-05-21 南通富士通微电子股份有限公司 芯片级封装方法
CN105409005A (zh) * 2013-08-23 2016-03-16 英特尔公司 在mos晶体管的iv族衬底上沉积的iii-v沟道的高阻层

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5684230B2 (ja) * 2009-04-08 2015-03-11 エフィシエント パワー コンヴァーション コーポレーション 電気的に絶縁された裏面を有するバンプ付き自己分離型ＧａＮトランジスタチップ
US10685904B2 (en) 2014-11-21 2020-06-16 Delta Electronics, Inc. Packaging device and manufacturing method thereof
US9324819B1 (en) 2014-11-26 2016-04-26 Delta Electronics, Inc. Semiconductor device
CN104780701A (zh) * 2015-04-17 2015-07-15 浪潮电子信息产业股份有限公司 一种简化pcb设计的散热装置
US10069002B2 (en) 2016-07-20 2018-09-04 Semiconductor Components Industries, Llc Bond-over-active circuity gallium nitride devices
WO2019021720A1 (ja) 2017-07-24 2019-01-31 株式会社村田製作所 半導体装置及び半導体装置の製造方法
KR102633137B1 (ko) 2018-01-23 2024-02-02 삼성전자주식회사 반도체 패키지
TWI683370B (zh) * 2019-03-12 2020-01-21 環球晶圓股份有限公司 半導體元件及其製造方法

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1254443A (zh) * 1997-03-26 2000-05-24 株式会社日立制作所 扁平型半导体装置和使用该装置的电力变换装置
US6269014B1 (en) * 1999-07-27 2001-07-31 Infineon Technologies Ag Half-bridge configuration
JP2004312993A (ja) * 2003-04-01 2004-11-04 Siemens Ag Ｄｃ／ｄｃコンバータ用電流検出回路
JP2005033130A (ja) * 2003-07-11 2005-02-03 Denso Corp 半導体装置
US20050145851A1 (en) * 2003-12-17 2005-07-07 Nitronex Corporation Gallium nitride material structures including isolation regions and methods
CN1757119A (zh) * 2003-01-02 2006-04-05 美商克立股份有限公司 以第三族氮化物为基的倒装片集成电路及其制造方法
US20060220042A1 (en) * 2005-03-31 2006-10-05 Eudyna Devices Inc. Semiconductor device and fabrication method of the same
US20080087915A1 (en) * 2006-10-12 2008-04-17 Yasuhiro Uemoto Nitride semiconductor device and method for fabricating the same
CN101272096A (zh) * 2006-12-11 2008-09-24 国际整流器公司 单片集成的ⅲ族氮化物功率转换器
US7491627B2 (en) * 2003-12-05 2009-02-17 International Rectifier Corporation III-nitride device and method with variable epitaxial growth direction
US7745848B1 (en) * 2007-08-15 2010-06-29 Nitronex Corporation Gallium nitride material devices and thermal designs thereof

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0513768A (ja) * 1991-07-08 1993-01-22 Fuji Electric Co Ltd 絶縁ゲート型バイポーラトランジスタ
JPH10256533A (ja) * 1997-03-17 1998-09-25 Toshiba Corp 化合物半導体装置およびその製造方法
US6452261B1 (en) * 1997-03-26 2002-09-17 Hitachi, Ltd. Flat semiconductor device and power converter employing the same
US6683384B1 (en) * 1997-10-08 2004-01-27 Agere Systems Inc Air isolated crossovers
US20020105009A1 (en) * 2000-07-13 2002-08-08 Eden Richard C. Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor
JP2002110799A (ja) * 2000-09-27 2002-04-12 Toshiba Corp 半導体装置及びその製造方法
JP3520039B2 (ja) * 2000-10-05 2004-04-19 三洋電機株式会社 半導体装置および半導体モジュール
US7071552B2 (en) * 2004-03-29 2006-07-04 Intel Corporation IC die with directly bonded liquid cooling device
JP4946262B2 (ja) * 2006-08-18 2012-06-06 富士通セミコンダクター株式会社 半導体素子の実装方法及び半導体装置の製造方法
JP2008117934A (ja) * 2006-11-02 2008-05-22 Nec Corp 半導体装置
US7863877B2 (en) * 2006-12-11 2011-01-04 International Rectifier Corporation Monolithically integrated III-nitride power converter
JP5684230B2 (ja) * 2009-04-08 2015-03-11 エフィシエント パワー コンヴァーション コーポレーション 電気的に絶縁された裏面を有するバンプ付き自己分離型ＧａＮトランジスタチップ

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1254443A (zh) * 1997-03-26 2000-05-24 株式会社日立制作所 扁平型半导体装置和使用该装置的电力变换装置
US6269014B1 (en) * 1999-07-27 2001-07-31 Infineon Technologies Ag Half-bridge configuration
CN1757119A (zh) * 2003-01-02 2006-04-05 美商克立股份有限公司 以第三族氮化物为基的倒装片集成电路及其制造方法
JP2004312993A (ja) * 2003-04-01 2004-11-04 Siemens Ag Ｄｃ／ｄｃコンバータ用電流検出回路
JP2005033130A (ja) * 2003-07-11 2005-02-03 Denso Corp 半導体装置
US7491627B2 (en) * 2003-12-05 2009-02-17 International Rectifier Corporation III-nitride device and method with variable epitaxial growth direction
US20050145851A1 (en) * 2003-12-17 2005-07-07 Nitronex Corporation Gallium nitride material structures including isolation regions and methods
US20060220042A1 (en) * 2005-03-31 2006-10-05 Eudyna Devices Inc. Semiconductor device and fabrication method of the same
US20080087915A1 (en) * 2006-10-12 2008-04-17 Yasuhiro Uemoto Nitride semiconductor device and method for fabricating the same
CN101272096A (zh) * 2006-12-11 2008-09-24 国际整流器公司 单片集成的ⅲ族氮化物功率转换器
US7745848B1 (en) * 2007-08-15 2010-06-29 Nitronex Corporation Gallium nitride material devices and thermal designs thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681858A (zh) * 2012-09-19 2014-03-26 株式会社东芝 半导体装置
CN105409005A (zh) * 2013-08-23 2016-03-16 英特尔公司 在mos晶体管的iv族衬底上沉积的iii-v沟道的高阻层
CN105409005B (zh) * 2013-08-23 2019-04-02 英特尔公司 在mos晶体管的iv族衬底上沉积的iii-v沟道的高阻层
CN103811365A (zh) * 2014-01-23 2014-05-21 南通富士通微电子股份有限公司 芯片级封装方法

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