JP5683600B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
- Publication number
- JP5683600B2 JP5683600B2 JP2012539605A JP2012539605A JP5683600B2 JP 5683600 B2 JP5683600 B2 JP 5683600B2 JP 2012539605 A JP2012539605 A JP 2012539605A JP 2012539605 A JP2012539605 A JP 2012539605A JP 5683600 B2 JP5683600 B2 JP 5683600B2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- relay
- lead frame
- semiconductor device
- die pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 9
- 230000000052 comparative effect Effects 0.000 description 9
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- 239000010931 gold Substances 0.000 description 7
- 230000007257 malfunction Effects 0.000 description 6
- 238000007747 plating Methods 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 238000002788 crimping Methods 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
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Classifications
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49537—Plurality of lead frames mounted in one device
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- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
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- B29C45/14221—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles the inserts being deformed or preformed, e.g. by the injection pressure by tools, e.g. cutting means
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
- B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
- B29C45/00—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
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- B29C45/14639—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components
- B29C45/14655—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components connected to or mounted on a carrier, e.g. lead frame
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Description
樹脂封止型半導体装置としては、図21に示すように、パワー素子31を搭載した第1リードフレーム32と、パワー素子31を制御する制御素子33を搭載した第2リードフレーム34を三次元的に配置して樹脂封止することにより、小型化、軽量化を図ろうとしている半導体装置35がある(例えば、特許文献1参照)。
本発明は、前述の従来の課題を解決し、従来よりも信頼性の高い半導体装置を提供することを目的とする。
図1,図2,図3は、本実施の形態1の樹脂封止型の半導体装置を示す図である。
図1は、本発明の実施の形態1にかかる樹脂封止型の半導体装置の内部の平面図である。図2は、図1におけるA−A断面図を示し、図3は図1におけるB−B断面図を示している。
第1リードフレーム1は、例えば銅(Cu)などの高い導電性の材料で構成される。第1リードフレーム1は、外装体4から端部が突出した複数の第1外部接続リード1a1,1a2,1a3,1a4と、複数の第1中継リード1bと、パワー素子T1が搭載された第1ダイパット部1cを有している。
この実施の形態1では、第2リードフレーム2が第1リードフレーム1の少なくとも一部を覆うように配置されているので、パワー素子T1から発生する電磁波ノイズを、制御素子T2の下面に設置した第2リードフレーム2により遮蔽することができる。その結果、制御素子T2に到達する電磁波ノイズ量は減少する。よって、制御素子T2の誤動作の可能性を軽減し、その動作に対する信頼性を高めることができる。
図4において、まず、ステップS1において、第1工程として、第1リードフレーム1及び第2リードフレーム2を準備した後、図5に示すホルダー11,12間に配置する。
続いて、ステップS3において、第3工程として、第1リードフレーム1及び第2リードフレーム2を、カシメピン13A,13Bでかしめて、カシメ接合する。
図5に示すように、先ず、ホルダー11とホルダー12の間において、ホルダー11上に絶縁シート5を仮接着した放熱板3を載置する。そして、第1リードフレーム1の第1ダイパッド部1cの下面および第1中継リード1bの下面が絶縁シート5に接するように、第1リードフレーム1を放熱板3の上に載置する。
第1リードフレーム1の具体例を図14に示す。2点鎖線で示す外装体4の位置が、封止予定位置である。1a1〜1a5が、図1〜図3に示した第1外部接続リード1a1〜1a4に相当する。図1〜図3では、第1中継リード1bが、第2リードフレーム2の引き出し側( = 外装体4の長辺4bの側 )に近接して配置されていたが、図7に示した具体例では、第1中継リード1b1〜1b9が第1外部接続リード1a1〜1a5と同じ側に配置されている。この実施の形態1の半導体装置では、図14に示すように、特に、半導体装置となったときに沿面絶縁距離が必要となる第1外部接続リード1a4と第1外部接続リード1a5の間に、第1中継リード1b4〜1b9が集中的に配置されている。
図6は、図4の第2工程における半導体装置の状態を示している。
図7に示すように、第1リードフレーム1と第2リードフレーム2の位置をホルダー11,12で挟持して保持した状態で、押圧ピン14Aとカシメピン13Aを下降させる。ここで、この実施の形態1では、押圧ピン14Aの下降速度をカシメピン13Aの下降速度より速くしている。これは、本実施の形態1では、カシメピン13Aが凸部1d1をかしめる前に、押圧ピン14Aにより第1リードフレーム1の位置を押圧して固定するためである。そして、押圧ピン14Aにより第1リードフレーム1が固定された状態で、第1中継リード1bの凸部1d1をカシメピン13Aによって押し潰してカシメ部1dを形成し、第1リードフレーム1と第2リードフレーム2を接合する。
図8に示すように、前述の第3工程において、形成されたカシメ部1dによって第1中継リード1bと一端が接続された第2中継リード2b、ならびに、第2ダイパット部2cの吊りリード2eを、切断ピン15Aとダイ15Bによって挟み込んで切断する。このとき、第2中継リード2bは、カシメ部1dとホルダー11,12間で保持されているため、切断ピン15Aとダイ15Bによって切断可能である。また、同様に、吊りリード2eは、カシメ部1gとホルダー11,12間で保持されているため、切断ピン15Aとダイ15Bによって切断可能である。
図10に示すように、図4の第4工程までの工程を経て一体化された第1リードフレーム1と第2リードフレーム2を、下金型16と上金型17によって上下から挟みこんで固定する。
図11に示すように、下金型16及び上金型17に形成されたキャビティ18に対して、上金型17のゲート口17Bから、エポキシ等の封止樹脂20を注入する。このようにキャビティ18内に封止樹脂20を注入し、トランスファーモールド法により外装体4を形成する。このとき、第1リードフレーム1は、上金型17のゲート口17B側(図11の紙面左側)に配置された金型挿入ピン19によって下金型16に押圧されているので、ゲート口17B側において、封止樹脂20が放熱板3の下面側に漏れ出して入り込むことはない。また、ゲート口17Bの反対側(図11の紙面右側)は、注入される封止樹脂20により下金型16に押圧されることになるので、ゲート口17Bの反対側において、封止樹脂20が放熱板3の下面側に漏れ出して入り込むことは無い。したがって、封止後の放熱板3の下面側には、封止樹脂20が存在せず、放熱性の低下は発生しない。
図13は比較例としての樹脂封止型の半導体装置を示す。
図1に示した実施の形態1の半導体装置では、第2中継リード2bの端部2dと第2ダイパット部2cの吊りリード2eとを切断してから樹脂で封止して、外装体4を形成している。それに対し、この比較例の半導体装置では、第2中継リード2bの端部と第2ダイパット部2cの吊りリード2eとを切断せずに樹脂封止して外装体4を形成した後に、外装体4の外部で全ての吊りリードを切断している。比較例は、このように、第2中継リード2bと吊りリード2eの切断のタイミングが、実施の形態1とは異なっている。
ここで、実施の形態1の半導体装置と比較例の半導体装置との比較を行う。
図18〜図20は実施の形態2を示す。
実施の形態1では、第2リードフレーム2の第2中継リード2bなどを切断する際、図7と図8に示すように、切断ピン15Aを上側から下側に動かして第2リードフレーム2を貫通させた。だが、この実施の形態2では、第2リードフレーム2の第2中継リード2bなどを切断する際、図18と図19に示すように、切断ピン15Aを下側から上側に動かして第2リードフレーム2を貫通させている。この実施の形態2は、このように、切断ピン15Aを動かして第2リードフレーム2を切断する方向が、実施の形態1とは異なっている。
T2 制御素子
1 第1リードフレーム
1a1,1a2,1a3,1a4,1a5 第1外部接続リード
1b 第1中継リード
1c 第1ダイパット部
1d,1g カシメ部
1d1,1g1 凸部
2 第2リードフレーム
2a1,2a2,2a3,2a4,2a5,2a6 第2外部接続リード
2b 第2中継リード
2c 第2ダイパット部
2d 端部
2e 吊りリード
2f 貫通孔
2g 突出部
3 放熱板
3C 角部
4 外装体
4a,4b 長辺
5 絶縁シート
6 ろう材
7,8a,8b,10 ワイヤ
9 接合部
11,12 ホルダー
13A,13B カシメピン
14A,14B 押圧ピン
15A 切断ピン
15B ダイ
16 下金型
17 上金型
17B ゲート口
18 キャビティ
19 金型挿入ピン
20 封止樹脂
21 反り返り部
Claims (11)
- 樹脂製の外装体と、
第1中継リードと、第1半導体チップが搭載された第1ダイパット部と、前記外装体から端部が突出した第1外部接続リードとを有する第1リードフレームと、
第2中継リードと、第2半導体チップが搭載された第2ダイパット部と、前記外装体から端部が突出した第2外部接続リードとを有する第2リードフレームと、を有し、
前記外装体は、前記第1半導体チップおよび前記第2半導体チップを1つのパッケージで封止しており、
前記第1ダイパット部と前記第2ダイパット部とが第1接合部で接合し、前記第1中継リードと前記第2中継リードとが第2接合部で接合して電気接続され、
前記第2接合部から延びる前記第2中継リードの端部と、前記第2ダイパット部の吊りリードの端部とが、前記外装体の内部に位置し、
前記第1リードフレームの上に前記第2リードフレームが積層され、
前記第1中継リードと前記第1半導体チップとの間がワイヤで電気接続され、前記第1中継リードに前記第2接合部で電気接続された前記第2中継リードと前記第2半導体チップとの間がワイヤで電気接続された
半導体装置。 - 前記第1半導体チップの少なくとも一部と前記第2半導体チップの少なくとも一部とは、平面視で互いに重なるように配置された、
請求項1に記載の半導体装置。 - 前記第1リードフレームの前記第1中継リードと、前記第2リードフレームの前記第2中継リードとが、カシメ接合によって接合された、
請求項1または請求項2に記載の半導体装置。 - 前記第1リードフレームの前記第1中継リードと、前記第2リードフレームの前記第2中継リードとが、面接合によって接合された、
請求項1または請求項2に記載の半導体装置。 - 前記外装体の表面から一部が露出した放熱板に、前記第1リードフレームの前記第1中継リードと前記第1ダイパット部が結合された、
請求項1〜請求項4のいずれかに記載の半導体装置。 - 第1中継リード及び前記第1半導体チップが搭載された第1ダイパット部及び第1外部接続リードを有する第1リードフレームと、第2中継リード及び第2半導体チップが搭載された第2ダイパット部及び第2外部接続リードを有する第2リードフレームとを準備し、
前記第1ダイパット部と前記第2ダイパット部を接合し、前記第1中継リードと前記第2中継リードを接合して電気接続した後、
前記第1中継リードとの接合部から延びる前記第2リードフレームの前記第2中継リード、または前記第2ダイパット部の吊りリードを、樹脂製の外装体による封止予定位置の半導体パッケージ内部位置で切断し、
切断された前記第2リードフレームの端部または切断された吊りリードの端部を金型の内部に配置した状態で、樹脂封止によって前記外装体を形成する、
半導体装置の製造方法。 - 前記第1半導体チップの少なくとも一部と前記第2半導体チップの少なくとも一部とは、平面視で互いに重なるように配置された、
請求項6に記載の半導体装置の製造方法。 - 前記第1リードフレームの前記第1中継リードと、前記第2リードフレームの前記第2中継リードとを、カシメ接合によって接合した、
請求項6または請求項7に記載の半導体装置の製造方法。 - 前記第1リードフレームの前記第1中継リードと、前記第2リードフレームの前記第2中継リードとを、面接合によって接合した、
請求項6または請求項7に記載の半導体装置の製造方法。 - 前記第2中継リードまたは前記吊りリードを切断した後に、前記第1リードフレームの前記第1中継リードと前記第1ダイパット部とを放熱板に結合する、
請求項6〜請求項9のいずれかに記載の半導体装置の製造方法。 - 前記第1ダイパット部と前記第2ダイパット部、または、前記第1中継リードと前記第2中継リードを接合する前に、前記第1リードフレームの前記第1中継リードと前記第1ダイパット部とを放熱板に結合する、
請求項6〜請求項10のいずれかに記載の半導体装置の製造方法。
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JP6178555B2 (ja) * | 2012-09-07 | 2017-08-09 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法および半導体装置 |
WO2014045435A1 (ja) * | 2012-09-24 | 2014-03-27 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法および半導体装置 |
US20140110833A1 (en) * | 2012-10-24 | 2014-04-24 | Samsung Electro-Mechanics Co., Ltd. | Power module package |
WO2014076856A1 (ja) * | 2012-11-19 | 2014-05-22 | 富士電機株式会社 | 半導体装置 |
CN105765711A (zh) * | 2013-12-23 | 2016-07-13 | 英特尔公司 | 封装体叠层架构以及制造方法 |
CN105336631B (zh) * | 2014-06-04 | 2019-03-01 | 恩智浦美国有限公司 | 使用两个引线框架组装的半导体装置 |
EP3186552B2 (en) * | 2014-08-28 | 2023-08-30 | Signify Holding B.V. | Lighting fixture |
JP6522402B2 (ja) * | 2015-04-16 | 2019-05-29 | ローム株式会社 | 半導体装置 |
JP6275292B1 (ja) * | 2016-03-11 | 2018-02-07 | 新電元工業株式会社 | 半導体装置及びその製造方法 |
JP6673012B2 (ja) * | 2016-05-26 | 2020-03-25 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
US10074590B1 (en) * | 2017-07-02 | 2018-09-11 | Infineon Technologies Ag | Molded package with chip carrier comprising brazed electrically conductive layers |
CN109214252B (zh) * | 2017-07-06 | 2021-11-09 | 敦泰电子有限公司 | 一种指纹感测电路及指纹感测装置 |
CN107785279A (zh) * | 2017-10-18 | 2018-03-09 | 天津力芯伟业科技有限公司 | 一种电子碳化硅芯片 |
CN112219352B (zh) * | 2018-06-04 | 2024-06-04 | 罗姆股份有限公司 | 半导体器件 |
JP7298177B2 (ja) * | 2019-02-15 | 2023-06-27 | 富士電機株式会社 | 半導体モジュール及び半導体モジュールの製造方法 |
CN114008771A (zh) * | 2019-07-02 | 2022-02-01 | 三菱电机株式会社 | 功率模块及其制造方法 |
EP4053887A1 (en) * | 2021-03-05 | 2022-09-07 | Infineon Technologies AG | Method and device for producing a housing |
CN116441752B (zh) * | 2023-04-27 | 2023-11-21 | 广州丰江微电子有限公司 | 高精度定位引线框架切割系统 |
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- 2011-10-20 CN CN201180005243.9A patent/CN102714202B/zh not_active Expired - Fee Related
- 2011-10-20 WO PCT/JP2011/005865 patent/WO2012053205A1/ja active Application Filing
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US8987877B2 (en) | 2015-03-24 |
EP2631942A1 (en) | 2013-08-28 |
CN102714202A (zh) | 2012-10-03 |
US20130015567A1 (en) | 2013-01-17 |
CN102714202B (zh) | 2015-08-12 |
US20140264801A1 (en) | 2014-09-18 |
JPWO2012053205A1 (ja) | 2014-02-24 |
EP2631942A4 (en) | 2014-11-12 |
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EP2631942B1 (en) | 2019-02-27 |
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