JP5664592B2 - 貼り合わせウェーハの製造方法 - Google Patents

貼り合わせウェーハの製造方法 Download PDF

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Publication number
JP5664592B2
JP5664592B2 JP2012101768A JP2012101768A JP5664592B2 JP 5664592 B2 JP5664592 B2 JP 5664592B2 JP 2012101768 A JP2012101768 A JP 2012101768A JP 2012101768 A JP2012101768 A JP 2012101768A JP 5664592 B2 JP5664592 B2 JP 5664592B2
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JP
Japan
Prior art keywords
wafer
plasma activation
stage
bonded
bond
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Active
Application number
JP2012101768A
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English (en)
Japanese (ja)
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JP2013229516A (ja
JP2013229516A5 (https=
Inventor
徹 石塚
徹 石塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Priority to JP2012101768A priority Critical patent/JP5664592B2/ja
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Priority to CN201380021381.5A priority patent/CN104246971B/zh
Priority to EP13781764.9A priority patent/EP2843686B1/en
Priority to KR1020147029823A priority patent/KR101855812B1/ko
Priority to SG11201406661YA priority patent/SG11201406661YA/en
Priority to PCT/JP2013/002278 priority patent/WO2013161188A1/ja
Priority to US14/391,086 priority patent/US9142449B2/en
Publication of JP2013229516A publication Critical patent/JP2013229516A/ja
Publication of JP2013229516A5 publication Critical patent/JP2013229516A5/ja
Application granted granted Critical
Publication of JP5664592B2 publication Critical patent/JP5664592B2/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32412—Plasma immersion ion implantation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05H—PLASMA TECHNIQUE; PRODUCTION OF ACCELERATED ELECTRICALLY-CHARGED PARTICLES OR OF NEUTRONS; PRODUCTION OR ACCELERATION OF NEUTRAL MOLECULAR OR ATOMIC BEAMS
    • H05H1/00—Generating plasma; Handling plasma
    • H05H1/24—Generating plasma
    • H05H1/46—Generating plasma using applied electromagnetic fields, e.g. high frequency or microwave energy
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/10—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/76—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches
    • H10P72/7604—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support
    • H10P72/7614—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a plurality of individual support members, e.g. support posts or protrusions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/10—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H10P70/15—Cleaning before device manufacture, i.e. Begin-Of-Line process by wet cleaning only

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Electromagnetism (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
JP2012101768A 2012-04-26 2012-04-26 貼り合わせウェーハの製造方法 Active JP5664592B2 (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2012101768A JP5664592B2 (ja) 2012-04-26 2012-04-26 貼り合わせウェーハの製造方法
EP13781764.9A EP2843686B1 (en) 2012-04-26 2013-04-02 Method of manufacturing bonded wafer
KR1020147029823A KR101855812B1 (ko) 2012-04-26 2013-04-02 접합웨이퍼의 제조방법
SG11201406661YA SG11201406661YA (en) 2012-04-26 2013-04-02 Method for manufacturing bonded wafer
CN201380021381.5A CN104246971B (zh) 2012-04-26 2013-04-02 贴合晶片的制造方法
PCT/JP2013/002278 WO2013161188A1 (ja) 2012-04-26 2013-04-02 貼り合わせウェーハの製造方法
US14/391,086 US9142449B2 (en) 2012-04-26 2013-04-02 Method for manufacturing bonded wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012101768A JP5664592B2 (ja) 2012-04-26 2012-04-26 貼り合わせウェーハの製造方法

Publications (3)

Publication Number Publication Date
JP2013229516A JP2013229516A (ja) 2013-11-07
JP2013229516A5 JP2013229516A5 (https=) 2014-12-11
JP5664592B2 true JP5664592B2 (ja) 2015-02-04

Family

ID=49482543

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012101768A Active JP5664592B2 (ja) 2012-04-26 2012-04-26 貼り合わせウェーハの製造方法

Country Status (7)

Country Link
US (1) US9142449B2 (https=)
EP (1) EP2843686B1 (https=)
JP (1) JP5664592B2 (https=)
KR (1) KR101855812B1 (https=)
CN (1) CN104246971B (https=)
SG (1) SG11201406661YA (https=)
WO (1) WO2013161188A1 (https=)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6213046B2 (ja) * 2013-08-21 2017-10-18 信越半導体株式会社 貼り合わせウェーハの製造方法
CN112053991B (zh) * 2014-05-21 2022-04-15 应用材料公司 热处理基座
JP6638282B2 (ja) * 2015-09-25 2020-01-29 三菱マテリアル株式会社 冷却器付き発光モジュールおよび冷却器付き発光モジュールの製造方法
US10269756B2 (en) 2017-04-21 2019-04-23 Invensas Bonding Technologies, Inc. Die processing
JP6686962B2 (ja) * 2017-04-25 2020-04-22 信越半導体株式会社 貼り合わせウェーハの製造方法
CN107633997B (zh) 2017-08-10 2019-01-29 长江存储科技有限责任公司 一种晶圆键合方法
US10727219B2 (en) * 2018-02-15 2020-07-28 Invensas Bonding Technologies, Inc. Techniques for processing devices
JP2018201033A (ja) * 2018-08-02 2018-12-20 株式会社ニコン 接合方法および接合装置
CN109671664A (zh) * 2018-12-14 2019-04-23 北京半导体专用设备研究所（中国电子科技集团公司第四十五研究所） 晶圆载片台
US11742314B2 (en) 2020-03-31 2023-08-29 Adeia Semiconductor Bonding Technologies Inc. Reliable hybrid bonded apparatus
US11257902B2 (en) * 2020-05-28 2022-02-22 Taiwan Semiconductor Manufacturing Company Limited SOI device structure for robust isolation
US12550799B2 (en) 2021-03-31 2026-02-10 Adeia Semiconductor Bonding Technologies Inc. Direct bonding methods and structures
US12604771B2 (en) 2021-10-28 2026-04-14 Adeia Semiconductor Bonding Technologies Inc. Direct bonding methods and structures

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56135934A (en) * 1980-03-27 1981-10-23 Chiyou Lsi Gijutsu Kenkyu Kumiai Dry etching device
JP3134391B2 (ja) * 1991-09-19 2001-02-13 株式会社デンソー シリコン基板の接合方法
US6534380B1 (en) * 1997-07-18 2003-03-18 Denso Corporation Semiconductor substrate and method of manufacturing the same
DE19929278A1 (de) * 1998-06-26 2000-02-17 Nissin Electric Co Ltd Verfahren zum Implantieren negativer Wasserstoffionen und Implantierungseinrichtung
KR100730806B1 (ko) * 1999-10-14 2007-06-20 신에쯔 한도타이 가부시키가이샤 Ｓｏｉ웨이퍼의 제조방법 및 ｓｏｉ 웨이퍼
JP3626933B2 (ja) 2001-02-08 2005-03-09 東京エレクトロン株式会社 基板載置台の製造方法
US7176528B2 (en) * 2003-02-18 2007-02-13 Corning Incorporated Glass-based SOI structures
JP4509488B2 (ja) * 2003-04-02 2010-07-21 株式会社Sumco 貼り合わせ基板の製造方法
JP2006339363A (ja) 2005-06-01 2006-12-14 Bondtech Inc 表面活性化方法および表面活性化装置
JP2007173354A (ja) * 2005-12-20 2007-07-05 Shin Etsu Chem Co Ltd Ｓｏｉ基板およびｓｏｉ基板の製造方法
US7791708B2 (en) * 2006-12-27 2010-09-07 Asml Netherlands B.V. Lithographic apparatus, substrate table, and method for enhancing substrate release properties
JP5433927B2 (ja) * 2007-03-14 2014-03-05 株式会社Ｓｕｍｃｏ 貼り合わせウェーハの製造方法
JP5415676B2 (ja) * 2007-05-30 2014-02-12 信越化学工業株式会社 Ｓｏｉウェーハの製造方法
JP4577382B2 (ja) 2008-03-06 2010-11-10 信越半導体株式会社 貼り合わせウェーハの製造方法
EP2200077B1 (en) * 2008-12-22 2012-12-05 Soitec Method for bonding two substrates
US8557679B2 (en) * 2010-06-30 2013-10-15 Corning Incorporated Oxygen plasma conversion process for preparing a surface for bonding
JP2012038963A (ja) 2010-08-09 2012-02-23 Sumco Corp 貼り合わせウェーハの製造方法

Also Published As

Publication number Publication date
US20150118825A1 (en) 2015-04-30
EP2843686A1 (en) 2015-03-04
SG11201406661YA (en) 2014-11-27
JP2013229516A (ja) 2013-11-07
CN104246971B (zh) 2018-06-15
WO2013161188A1 (ja) 2013-10-31
CN104246971A (zh) 2014-12-24
EP2843686A4 (en) 2016-01-20
EP2843686B1 (en) 2019-03-27
KR20150003763A (ko) 2015-01-09
US9142449B2 (en) 2015-09-22
KR101855812B1 (ko) 2018-05-10

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