JP5614440B2 - 回路部品及びその製造方法 - Google Patents
回路部品及びその製造方法 Download PDFInfo
- Publication number
- JP5614440B2 JP5614440B2 JP2012236903A JP2012236903A JP5614440B2 JP 5614440 B2 JP5614440 B2 JP 5614440B2 JP 2012236903 A JP2012236903 A JP 2012236903A JP 2012236903 A JP2012236903 A JP 2012236903A JP 5614440 B2 JP5614440 B2 JP 5614440B2
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- Japan
- Prior art keywords
- substrate
- chip
- conductive particles
- electrode
- bump electrode
- Prior art date
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- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/81401—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
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- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
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- H01L2924/14—Integrated circuits
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- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
Description
図1は実施形態に係る回路部品が適用された電子機器を示す平面図、図2は図1の回路部品を示す平面図、図3は図2中のIII-III矢視断面を示す模式断面図である。なお、図3においては、後述する導電性接着剤5に含有されている導電粒子の図示は省略されている。
次に、ガラス基板31とICチップ4とを接続する導電性接着剤5について詳細に説明する。導電性接着剤5の接着剤成分としては、熱や光により硬化性を示す材料が広く適用でき、例えばエポキシ系接着剤やアクリル系接着剤を使用できる。また、接続後の耐熱性や耐湿性に優れていることから、架橋性材料の使用が好ましい。なかでも熱硬化性樹脂であるエポキシ樹脂を主成分として含有するエポキシ系接着剤は、短時間での硬化が可能で接続作業性がよく、分子構造上接着性に優れている等の特徴から好ましい。
次に、回路部品1において、基板31とICチップ4との間に介在している導電粒子について詳細に説明する。図4は図3中のA部を示す断面図、図5は図3中のB部を示す断面図である。
次に、回路部品の製造方法について説明する。
Claims (7)
- 導電粒子を含有する導電性接着剤によってICチップを基板に接続してなる回路部品であって、
前記ICチップの実装面には、バンプ電極と、前記バンプ電極が形成された部分を除く非電極面とが設けられ、
前記基板の表面と前記非電極面との間には、前記基板の表面及び前記非電極面の双方に接する第1の状態の導電粒子が存在し、
前記基板の表面と前記バンプ電極との間には、前記第1の状態よりも扁平な第2の状態で前記バンプ電極に食い込むように配置された導電粒子が存在することを特徴とする回路部品。 - 導電粒子を含有する導電性接着剤によってICチップを基板に接続してなる回路部品であって、
前記ICチップの実装面には、バンプ電極と、前記バンプ電極が形成された部分を除く非電極面とが設けられ、
前記基板の表面と前記非電極面との間には、前記バンプ電極の高さ方向の大きさが前記基板の表面と前記非電極面との間の間隔に一致している導電粒子が存在することを特徴とする回路部品。 - 前記基板は、ガラス基板であることを特徴とする請求項1又は2に記載の回路部品。
- 導電粒子を含有する導電性接着剤によってICチップを基板に接続する回路部品の製造方法であって、
前記基板の表面と前記ICチップとの間に、前記ICチップのバンプ電極の高さより大きい平均粒径の導電粒子を含有する導電性接着剤を介在させた後、前記基板と前記ICチップとを圧着させ、前記基板の表面と、前記ICチップの実装面において前記バンプ電極が形成された部分を除く非電極面との間に、前記基板の表面及び前記非電極面の双方に接する第1の状態の導電粒子を配置することを特徴とする回路部品の製造方法。 - 前記圧着前の前記導電性接着剤の厚さが、前記導電粒子の前記平均粒径の80%以上200%以下になるように前記導電性接着剤を介在させることを特徴とする請求項4に記載の回路部品の製造方法。
- 前記非電極面と、前記基板の表面との間の前記圧着後の間隔が、前記導電粒子のうち、粒径の大きさが上位1%となる導電粒子を除いた残りの導電粒子の最大粒径の70%以上100%以下になるように、前記基板と前記ICチップとを圧着させることを特徴とする請求項4又は5に記載の回路部品の製造方法。
- 前記圧着により前記バンプ電極と前記基板の表面との間に介在される導電粒子は、前記バンプ電極の高さ方向における前記圧着後の大きさが、前記導電粒子の前記平均粒径の15%以上80%以下になるように、前記基板と前記ICチップとを圧着させることを特徴とする請求項4〜6のいずれか1項に記載の回路部品の製造方法。
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JP6719529B2 (ja) * | 2018-11-08 | 2020-07-08 | デクセリアルズ株式会社 | 電子部品、接続体、接続体の製造方法及び電子部品の接続方法 |
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