JP5603166B2 - 電子デバイス、電子機器及び電子デバイスの製造方法 - Google Patents
電子デバイス、電子機器及び電子デバイスの製造方法 Download PDFInfo
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- JP5603166B2 JP5603166B2 JP2010186312A JP2010186312A JP5603166B2 JP 5603166 B2 JP5603166 B2 JP 5603166B2 JP 2010186312 A JP2010186312 A JP 2010186312A JP 2010186312 A JP2010186312 A JP 2010186312A JP 5603166 B2 JP5603166 B2 JP 5603166B2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders; Supports
- H03H9/10—Mounting in enclosures
- H03H9/1007—Mounting in enclosures for bulk acoustic wave [BAW] devices
- H03H9/1014—Mounting in enclosures for bulk acoustic wave [BAW] devices the enclosure being defined by a frame built on a substrate and a cap, the frame having no mechanical contact with the BAW device
- H03H9/1021—Mounting in enclosures for bulk acoustic wave [BAW] devices the enclosure being defined by a frame built on a substrate and a cap, the frame having no mechanical contact with the BAW device the BAW device being of the cantilever type
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
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- B81B7/0032—Packages or encapsulation
- B81B7/007—Interconnections between the MEMS and external electrical signals
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
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- H01L21/486—Via connections through the substrate with or without pins
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- H05K2201/10371—Shields or metal cases
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
Description
本発明の電子デバイスは、ガラスにより形成されたベースと、前記ベースを貫通する貫通電極と、前記貫通電極の前記ベースの1の面側の端面上に形成されるとともに、前記ベースの1の面上に形成された回路パターンと、前記貫通電極の前記ベースの1の面と反対の面側の端面上に形成されるとともに、前記ベースの1の面と反対の面上に形成された電極パターンと、前記貫通電極と電気的に接続し、前記回路パターン上を覆う内部配線と、前記内部配線と電気的に接続し、かつ前記内部配線上に形成された接続部と、前記空洞部に設けられ、前記接続部と電気的に接続し、かつ前記接続部に設置された電子部品と、前記貫通電極と電気的に接続し、前記電極パターン上に形成された外部電極とを備えることを特徴とする。
また、前記内部配線及び前記外部電極は、それぞれ単一の層で形成されていることを特徴とすることを特徴とする請求項1から5のいずれか一項に記載の電子デバイス。
また、本発明に係る電子デバイスを用いた電子機器を提供することができる。
図2(a)は、ベース10に貫通孔を形成する工程である。貫通孔は、サンドブラスト、レーザー加工、ドリル加工、熱プレス加工等で製造する。
10 ベース
20 貫通電極
21 切削された貫通電極
30 回路パターン
31 内部配線
40 電子部品
50 キャップ
61 電極パターン
60 外部電極
70 低融点ガラス
80 酸化膜
100 電子デバイス
110 ベース
120 金属ピン
130 電極
140 電子部品
150 封止材
160 キャップ
170 低融点ガラス
180 酸化膜
Claims (15)
- ガラスにより形成されたベースと、
前記ベースを貫通し、金属ピンで形成される貫通電極と、
前記貫通電極の前記ベースの1の面側の端面上に形成されるとともに、前記ベースの1の面上に形成された回路パターンと、
前記貫通電極の前記ベースの1の面と反対の面側の端面上に形成されるとともに、前記ベースの1の面と反対の面上に形成された電極パターンと、
前記貫通電極と電気的に接続し、前記回路パターンを覆う内部配線と、
前記内部配線と電気的に接続し、かつ前記内部配線上に形成された接続部と、
前記接続部と電気的に接続し、かつ前記接続部に設置された電子部品と、
前記貫通電極と電気的に接続し、前記電極パターンを覆う外部電極と、
を備え、
前記回路パターン及び前記電極パターンは、前記ベースの面上に形成された部分と異なる部分に凹部を有し、
前記内部配線及び前記外部電極は、前記凹部を埋めることを特徴とする電子デバイス。 - 前記回路パターンは、前記電極パターンと同一の材料で形成されることを特徴とする請求項1に記載の電子デバイス。
- 前記内部配線は、前記外部電極と同一の材料で形成されることを特徴とする請求項1または請求項2に記載の電子デバイス。
- 前記内部配線及び前記外部電極は、金属拡散を防止する拡散防止層と、前記拡散防止層上に形成され、最表面が金で形成された表面層とを備える金属膜で形成されることを特徴とする請求項3に記載の電子デバイス。
- 前記内部配線及び前記外部電極は、それぞれ単一の層で形成されていることを特徴とすることを特徴とする請求項1から3のいずれか一項に記載の電子デバイス。
- 前記回路パターン及び前記電極パターンはアルミニウムで形成されることを特徴とする請求項2に記載の電子デバイス。
- 前記拡散防止層は、ニッケルで形成されていることを特徴とする請求項4に記載の電子デバイス。
- 前記ベースの1の面と接合し、前記ベースとの間で外気と遮断された空洞部を形成するキャップを有することを特徴とする請求項1から7のいずれか一項に記載の電子デバイス。
- 前記キャップはアルミニウム、ガラス、シリコンのいずれかで形成されることを特徴とする請求項8に記載の電子デバイス。
- 請求項1から9のいずれか一項に記載の電子デバイスを用いた電子機器。
- ガラスにより形成されたベースと、前記ベースを貫通する貫通電極と、前記貫通電極の端面上に形成される回路パターン及び電極パターンと、前記回路パターンを覆う内部配線と、前記内部配線上に形成された接続部と、前記接続部に設置された電子部品と、前記電極パターンを覆う外部電極と、を備える電子デバイスの製造方法であって、
金属ピンで形成される前記貫通電極の端面を研磨し、前記前記貫通電極の端面に生成された酸化膜を除去する工程と、
前記貫通電極の前記ベースの1の面側の端面上と、前記ベースの前記1の面上とに前記回路パターンを形成するとともに、前記回路パターンにおいて前記ベースの前記1の面上に形成された部分と異なる部分に凹部を形成する回路パターン形成工程と、
前記貫通電極の前記ベースの前記1の面と反対の面側の端面上と、前記ベースの前記反対の面上とに前記電極パターンを形成するとともに、前記電極パターンにおいて前記ベースの前記反対の面上に形成された部分と異なる部分に凹部を形成する電極パターン形成工程と、
前記回路パターンの凹部を埋めるとともに、前記回路パターンを覆う前記内部配線を形成し、前記貫通電極と前記内部配線とを電気的に接続する内部配線形成工程と、
前記電極パターンの凹部を埋めるとともに、前記電極パターンを覆う前記外部電極を形成し、前記貫通電極と前記外部電極とを電気的に接続する外部電極形成工程と、
を備えることを特徴とする電子デバイスの製造方法。 - 前記内部配線形成工程と前記外部電極形成工程とを同一の方法を用いて同一の工程で形成することを特徴とする請求項11に記載の電子デバイスの製造方法。
- 前記回路パターン形成工程と前記電極パターン形成工程とを同一の方法を用いて同一の工程で形成することを特徴とする請求項11または請求項12に記載の電子デバイスの製造方法。
- 前記内部配線形成工程及び前記外部電極形成工程は、前記内部配線及び前記外部電極の少なくとも一方を無電解めっきで形成することを特徴とする請求項11から13のいずれか一項に記載の電子デバイスの製造方法。
- 前記電子部品接続工程の後、前記ベースの前記1の面とキャップとを接合し、前記ベースと前記キャップとの間で外気と遮断された空洞部を形成するとともに、前記空洞部に前記電子部品を設けるキャップ接合工程を備えることを特徴とする請求項11から14のいずれか一項に記載の電子デバイスの製造方法。
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