JP5567794B2 - Ｓｏｉ基板の作製方法 - Google Patents

Ｓｏｉ基板の作製方法 Download PDF

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Publication number
JP5567794B2
JP5567794B2 JP2009149861A JP2009149861A JP5567794B2 JP 5567794 B2 JP5567794 B2 JP 5567794B2 JP 2009149861 A JP2009149861 A JP 2009149861A JP 2009149861 A JP2009149861 A JP 2009149861A JP 5567794 B2 JP5567794 B2 JP 5567794B2
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Prior art keywords
single crystal
crystal semiconductor
substrate
insulating film
semiconductor layer
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JP2009149861A
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English (en)
Japanese (ja)
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JP2010034535A5 (enExample
JP2010034535A (ja
Inventor
慎也 笹川
求 倉田
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2009149861A priority Critical patent/JP5567794B2/ja
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Publication of JP2010034535A5 publication Critical patent/JP2010034535A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
JP2009149861A 2008-06-26 2009-06-24 Ｓｏｉ基板の作製方法 Expired - Fee Related JP5567794B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009149861A JP5567794B2 (ja) 2008-06-26 2009-06-24 Ｓｏｉ基板の作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2008167618 2008-06-26
JP2008167618 2008-06-26
JP2009149861A JP5567794B2 (ja) 2008-06-26 2009-06-24 Ｓｏｉ基板の作製方法

Publications (3)

Publication Number Publication Date
JP2010034535A JP2010034535A (ja) 2010-02-12
JP2010034535A5 JP2010034535A5 (enExample) 2012-07-26
JP5567794B2 true JP5567794B2 (ja) 2014-08-06

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Family Applications (1)

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JP2009149861A Expired - Fee Related JP5567794B2 (ja) 2008-06-26 2009-06-24 Ｓｏｉ基板の作製方法

Country Status (3)

Country Link
US (1) US8343849B2 (enExample)
JP (1) JP5567794B2 (enExample)
KR (1) KR101629193B1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018030666A1 (ko) * 2016-08-11 2018-02-15 에스케이실트론 주식회사 웨이퍼 및 그 제조방법
TWI814329B (zh) * 2016-12-23 2023-09-01 美商蘭姆研究公司 用於執行原子層蝕刻之多站處理工具

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JP2011077504A (ja) * 2009-09-02 2011-04-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
FR2973158B1 (fr) * 2011-03-22 2014-02-28 Soitec Silicon On Insulator Procédé de fabrication d'un substrat de type semi-conducteur sur isolant pour applications radiofréquences
CN105931967B (zh) 2011-04-27 2019-05-03 株式会社半导体能源研究所 半导体装置的制造方法
US20180347035A1 (en) 2012-06-12 2018-12-06 Lam Research Corporation Conformal deposition of silicon carbide films using heterogeneous precursor interaction
US10325773B2 (en) 2012-06-12 2019-06-18 Novellus Systems, Inc. Conformal deposition of silicon carbide films
US9234276B2 (en) 2013-05-31 2016-01-12 Novellus Systems, Inc. Method to obtain SiC class of films of desired composition and film properties
US12334332B2 (en) 2012-06-12 2025-06-17 Lam Research Corporation Remote plasma based deposition of silicon carbide films using silicon-containing and carbon-containing precursors
US10832904B2 (en) 2012-06-12 2020-11-10 Lam Research Corporation Remote plasma based deposition of oxygen doped silicon carbide films
JP6236753B2 (ja) * 2012-06-28 2017-11-29 株式会社豊田自動織機 半導体基板の製造方法
US10297442B2 (en) * 2013-05-31 2019-05-21 Lam Research Corporation Remote plasma based deposition of graded or multi-layered silicon carbide film
JP6200273B2 (ja) * 2013-10-17 2017-09-20 信越半導体株式会社 貼り合わせウェーハの製造方法
US9385087B2 (en) * 2013-10-18 2016-07-05 Globalfoundries Inc. Polysilicon resistor structure having modified oxide layer
CN104022018A (zh) * 2014-06-19 2014-09-03 无锡宏纳科技有限公司 一种干法刻蚀等离子损伤修复工艺
US20160314964A1 (en) 2015-04-21 2016-10-27 Lam Research Corporation Gap fill using carbon-based films
SG10201604524PA (en) * 2015-06-05 2017-01-27 Lam Res Corp ATOMIC LAYER ETCHING OF GaN AND OTHER III-V MATERIALS
US10002787B2 (en) 2016-11-23 2018-06-19 Lam Research Corporation Staircase encapsulation in 3D NAND fabrication
US10840087B2 (en) 2018-07-20 2020-11-17 Lam Research Corporation Remote plasma based deposition of boron nitride, boron carbide, and boron carbonitride films
KR20230085953A (ko) 2018-10-19 2023-06-14 램 리써치 코포레이션 갭 충진 (gapfill) 을 위한 도핑되거나 도핑되지 않은 실리콘 카바이드 증착 및 원격 수소 플라즈마 노출

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6159825A (en) * 1997-05-12 2000-12-12 Silicon Genesis Corporation Controlled cleavage thin film separation process using a reusable substrate
JP4379927B2 (ja) * 1998-05-27 2009-12-09 信越半導体株式会社 Ｓｏｉウエーハの製造方法およびｓｏｉウエーハ
US6563133B1 (en) * 2000-08-09 2003-05-13 Ziptronix, Inc. Method of epitaxial-like wafer bonding at low temperature and bonded structure
JP4772258B2 (ja) 2002-08-23 2011-09-14 シャープ株式会社 Ｓｏｉ基板の製造方法
US7119365B2 (en) 2002-03-26 2006-10-10 Sharp Kabushiki Kaisha Semiconductor device and manufacturing method thereof, SOI substrate and display device using the same, and manufacturing method of the SOI substrate
EP1662549B1 (en) * 2003-09-01 2015-07-29 SUMCO Corporation Method for manufacturing bonded wafer
JP4759919B2 (ja) * 2004-01-16 2011-08-31 セイコーエプソン株式会社 電気光学装置の製造方法
KR100567735B1 (ko) * 2004-05-15 2006-04-04 주식회사 한택 레이저를 이용한 고품질 soi웨이퍼 제조장치 및 방법
KR100898649B1 (ko) * 2004-05-28 2009-05-22 가부시키가이샤 섬코 Ｓｏｉ기판 및 그 제조방법
JP2006080314A (ja) * 2004-09-09 2006-03-23 Canon Inc 結合基板の製造方法
JP4977999B2 (ja) * 2005-11-21 2012-07-18 株式会社Ｓｕｍｃｏ 貼合せ基板の製造方法及びその方法で製造された貼合せ基板
JP2007194345A (ja) * 2006-01-18 2007-08-02 Canon Inc はり合わせ基板の製造方法、及びはり合わせ基板の製造装置
FR2896618B1 (fr) * 2006-01-23 2008-05-23 Soitec Silicon On Insulator Procede de fabrication d'un substrat composite
FR2896619B1 (fr) * 2006-01-23 2008-05-23 Soitec Silicon On Insulator Procede de fabrication d'un substrat composite a proprietes electriques ameliorees
US7598153B2 (en) * 2006-03-31 2009-10-06 Silicon Genesis Corporation Method and structure for fabricating bonded substrate structures using thermal processing to remove oxygen species
US8003483B2 (en) * 2008-03-18 2011-08-23 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018030666A1 (ko) * 2016-08-11 2018-02-15 에스케이실트론 주식회사 웨이퍼 및 그 제조방법
TWI814329B (zh) * 2016-12-23 2023-09-01 美商蘭姆研究公司 用於執行原子層蝕刻之多站處理工具

Also Published As

Publication number Publication date
US8343849B2 (en) 2013-01-01
KR20100002130A (ko) 2010-01-06
KR101629193B1 (ko) 2016-06-10
US20090325364A1 (en) 2009-12-31
JP2010034535A (ja) 2010-02-12

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