JP5548395B2 - Ｓｏｉ基板の作製方法 - Google Patents

Ｓｏｉ基板の作製方法 Download PDF

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Publication number
JP5548395B2
JP5548395B2 JP2009139952A JP2009139952A JP5548395B2 JP 5548395 B2 JP5548395 B2 JP 5548395B2 JP 2009139952 A JP2009139952 A JP 2009139952A JP 2009139952 A JP2009139952 A JP 2009139952A JP 5548395 B2 JP5548395 B2 JP 5548395B2
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Japan
Prior art keywords
oxide film
substrate
nitrogen
semiconductor
containing layer
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Expired - Fee Related
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JP2009139952A
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English (en)
Japanese (ja)
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JP2010034523A5 (enExample
JP2010034523A (ja
Inventor
英人 大沼
賢一郎 牧野
陽一 飯窪
雅晴 永井
愛子 志賀
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2009139952A priority Critical patent/JP5548395B2/ja
Publication of JP2010034523A publication Critical patent/JP2010034523A/ja
Publication of JP2010034523A5 publication Critical patent/JP2010034523A5/ja
Application granted granted Critical
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Electroluminescent Light Sources (AREA)
  • Recrystallisation Techniques (AREA)
JP2009139952A 2008-06-25 2009-06-11 Ｓｏｉ基板の作製方法 Expired - Fee Related JP5548395B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009139952A JP5548395B2 (ja) 2008-06-25 2009-06-11 Ｓｏｉ基板の作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2008166447 2008-06-25
JP2008166447 2008-06-25
JP2009139952A JP5548395B2 (ja) 2008-06-25 2009-06-11 Ｓｏｉ基板の作製方法

Publications (3)

Publication Number Publication Date
JP2010034523A JP2010034523A (ja) 2010-02-12
JP2010034523A5 JP2010034523A5 (enExample) 2012-06-21
JP5548395B2 true JP5548395B2 (ja) 2014-07-16

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Family Applications (1)

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JP2009139952A Expired - Fee Related JP5548395B2 (ja) 2008-06-25 2009-06-11 Ｓｏｉ基板の作製方法

Country Status (5)

Country Link
US (2) US7829432B2 (enExample)
JP (1) JP5548395B2 (enExample)
KR (1) KR101574138B1 (enExample)
TW (1) TWI538111B (enExample)
WO (1) WO2009157369A1 (enExample)

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JP2011077504A (ja) * 2009-09-02 2011-04-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
US20110147817A1 (en) * 2009-12-17 2011-06-23 Infineon Technologies Austria Ag Semiconductor component having an oxide layer
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JP5780234B2 (ja) 2012-12-14 2015-09-16 信越半導体株式会社 Ｓｏｉウェーハの製造方法
US20170062569A1 (en) * 2014-06-13 2017-03-02 Intel Corporation Surface encapsulation for wafer bonding
JP6471650B2 (ja) * 2015-08-27 2019-02-20 株式会社Sumco Ｓｏｉウェーハの製造方法およびｓｏｉウェーハ
JP6524862B2 (ja) 2015-08-27 2019-06-05 株式会社Sumco Ｓｏｉウェーハの製造方法およびｓｏｉウェーハ
CN106601615B (zh) * 2016-12-27 2020-05-15 上海新傲科技股份有限公司 提高键合强度的退火方法
CN117038572A (zh) * 2017-07-14 2023-11-10 太阳能爱迪生半导体有限公司 绝缘体上半导体结构的制造方法
US10686037B2 (en) 2018-07-19 2020-06-16 Vanguard International Semiconductor Corporation Semiconductor structure with insulating substrate and fabricating method thereof
TWI692874B (zh) * 2018-09-17 2020-05-01 世界先進積體電路股份有限公司 半導體結構以及製造方法
JP2024165393A (ja) * 2023-05-17 2024-11-28 信越半導体株式会社 接合基板の製造方法および半導体装置の製造方法

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Also Published As

Publication number Publication date
US8198173B2 (en) 2012-06-12
KR20110022663A (ko) 2011-03-07
US7829432B2 (en) 2010-11-09
US20110039395A1 (en) 2011-02-17
WO2009157369A1 (en) 2009-12-30
TWI538111B (zh) 2016-06-11
US20090325363A1 (en) 2009-12-31
TW201001630A (en) 2010-01-01
KR101574138B1 (ko) 2015-12-03
JP2010034523A (ja) 2010-02-12

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