TWI538111B - Soi基板的製造方法 - Google Patents

Soi基板的製造方法 Download PDF

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Publication number
TWI538111B
TWI538111B TW098121197A TW98121197A TWI538111B TW I538111 B TWI538111 B TW I538111B TW 098121197 A TW098121197 A TW 098121197A TW 98121197 A TW98121197 A TW 98121197A TW I538111 B TWI538111 B TW I538111B
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TW
Taiwan
Prior art keywords
substrate
oxide film
nitrogen
semiconductor
support substrate
Prior art date
Application number
TW098121197A
Other languages
English (en)
Chinese (zh)
Other versions
TW201001630A (en
Inventor
大沼英人
牧野賢一郎
飯窪陽一
永井雅晴
志賀愛子
Original Assignee
半導體能源研究所股份有限公司
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Publication date
Application filed by 半導體能源研究所股份有限公司 filed Critical 半導體能源研究所股份有限公司
Publication of TW201001630A publication Critical patent/TW201001630A/zh
Application granted granted Critical
Publication of TWI538111B publication Critical patent/TWI538111B/zh

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01Manufacture or treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6704Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Electroluminescent Light Sources (AREA)
  • Recrystallisation Techniques (AREA)
TW098121197A 2008-06-25 2009-06-24 Soi基板的製造方法 TWI538111B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008166447 2008-06-25

Publications (2)

Publication Number Publication Date
TW201001630A TW201001630A (en) 2010-01-01
TWI538111B true TWI538111B (zh) 2016-06-11

Family

ID=41444437

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098121197A TWI538111B (zh) 2008-06-25 2009-06-24 Soi基板的製造方法

Country Status (5)

Country Link
US (2) US7829432B2 (enExample)
JP (1) JP5548395B2 (enExample)
KR (1) KR101574138B1 (enExample)
TW (1) TWI538111B (enExample)
WO (1) WO2009157369A1 (enExample)

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JP5917036B2 (ja) 2010-08-05 2016-05-11 株式会社半導体エネルギー研究所 Soi基板の作製方法
US20120045883A1 (en) * 2010-08-23 2012-02-23 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing soi substrate
CN103477420B (zh) 2011-04-08 2016-11-16 Ev集团E·索尔纳有限责任公司 永久性粘合晶片的方法
JP2014096454A (ja) * 2012-11-08 2014-05-22 Tokyo Electron Ltd 有機半導体素子の製造方法、絶縁膜の形成方法、及び溶液
JP5780234B2 (ja) 2012-12-14 2015-09-16 信越半導体株式会社 Soiウェーハの製造方法
US20170062569A1 (en) * 2014-06-13 2017-03-02 Intel Corporation Surface encapsulation for wafer bonding
JP6471650B2 (ja) * 2015-08-27 2019-02-20 株式会社Sumco Soiウェーハの製造方法およびsoiウェーハ
JP6524862B2 (ja) 2015-08-27 2019-06-05 株式会社Sumco Soiウェーハの製造方法およびsoiウェーハ
CN106601615B (zh) * 2016-12-27 2020-05-15 上海新傲科技股份有限公司 提高键合强度的退火方法
CN117038572A (zh) * 2017-07-14 2023-11-10 太阳能爱迪生半导体有限公司 绝缘体上半导体结构的制造方法
US10686037B2 (en) 2018-07-19 2020-06-16 Vanguard International Semiconductor Corporation Semiconductor structure with insulating substrate and fabricating method thereof
TWI692874B (zh) * 2018-09-17 2020-05-01 世界先進積體電路股份有限公司 半導體結構以及製造方法
JP2024165393A (ja) * 2023-05-17 2024-11-28 信越半導体株式会社 接合基板の製造方法および半導体装置の製造方法

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Also Published As

Publication number Publication date
US8198173B2 (en) 2012-06-12
KR20110022663A (ko) 2011-03-07
US7829432B2 (en) 2010-11-09
US20110039395A1 (en) 2011-02-17
WO2009157369A1 (en) 2009-12-30
JP5548395B2 (ja) 2014-07-16
US20090325363A1 (en) 2009-12-31
TW201001630A (en) 2010-01-01
KR101574138B1 (ko) 2015-12-03
JP2010034523A (ja) 2010-02-12

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