JP5526529B2 - 積層半導体装置及び積層半導体装置の製造方法 - Google Patents

積層半導体装置及び積層半導体装置の製造方法 Download PDF

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Publication number
JP5526529B2
JP5526529B2 JP2008294913A JP2008294913A JP5526529B2 JP 5526529 B2 JP5526529 B2 JP 5526529B2 JP 2008294913 A JP2008294913 A JP 2008294913A JP 2008294913 A JP2008294913 A JP 2008294913A JP 5526529 B2 JP5526529 B2 JP 5526529B2
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semiconductor device
substrate
region
element region
insulating layer
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JP2008294913A
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Japanese (ja)
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JP2010123696A5 (https=
JP2010123696A (ja
Inventor
新吾 松岡
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Nikon Corp
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Nikon Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/218—Through-semiconductor vias, e.g. TSVs in silicon-on-insulator [SOI] wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
JP2008294913A 2008-11-18 2008-11-18 積層半導体装置及び積層半導体装置の製造方法 Active JP5526529B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008294913A JP5526529B2 (ja) 2008-11-18 2008-11-18 積層半導体装置及び積層半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008294913A JP5526529B2 (ja) 2008-11-18 2008-11-18 積層半導体装置及び積層半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2010123696A JP2010123696A (ja) 2010-06-03
JP2010123696A5 JP2010123696A5 (https=) 2012-12-06
JP5526529B2 true JP5526529B2 (ja) 2014-06-18

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JP (1) JP5526529B2 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3099906B2 (ja) 1990-04-27 2000-10-16 日本ビクター株式会社 光ピックアップ

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5533398B2 (ja) * 2010-07-27 2014-06-25 富士通セミコンダクター株式会社 半導体装置の製造方法
JP2014207252A (ja) * 2011-08-17 2014-10-30 株式会社村田製作所 半導体装置およびその製造方法ならびに携帯電話機
US20230026676A1 (en) * 2021-07-23 2023-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device structure and method of formation

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6098654A (ja) * 1983-11-02 1985-06-01 Nec Corp 半導体装置の製造方法
JP3770631B2 (ja) * 1994-10-24 2006-04-26 株式会社ルネサステクノロジ 半導体装置の製造方法
TW473914B (en) * 2000-01-12 2002-01-21 Ibm Buried metal body contact structure and method for fabricating SOI MOSFET devices
JP2002026283A (ja) * 2000-06-30 2002-01-25 Seiko Epson Corp 多層構造のメモリ装置及びその製造方法
KR100418089B1 (ko) * 2001-06-21 2004-02-11 주식회사 하이닉스반도체 반도체 소자의 박막 트랜지스터 제조 방법
JP4869546B2 (ja) * 2003-05-23 2012-02-08 ルネサスエレクトロニクス株式会社 半導体装置
JP4606006B2 (ja) * 2003-09-11 2011-01-05 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP5354765B2 (ja) * 2004-08-20 2013-11-27 カミヤチョウ アイピー ホールディングス 三次元積層構造を持つ半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3099906B2 (ja) 1990-04-27 2000-10-16 日本ビクター株式会社 光ピックアップ

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