JP5506825B2 - 面積および電力消費量が削減されたdfeのための回路および方法 - Google Patents
面積および電力消費量が削減されたdfeのための回路および方法 Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
- H03K3/35613—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/04—Control of transmission; Equalising
- H04B3/14—Control of transmission; Equalising characterised by the equalising network used
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/32—Reducing cross-talk, e.g. by compensating
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
- H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03114—Arrangements for removing intersymbol interference operating in the time domain non-adaptive, i.e. not adjustable, manually adjustable, or adjustable only during the reception of special signals
- H04L25/03146—Arrangements for removing intersymbol interference operating in the time domain non-adaptive, i.e. not adjustable, manually adjustable, or adjustable only during the reception of special signals with a recursive structure
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03178—Arrangements involving sequence estimation techniques
- H04L25/03248—Arrangements for operating in conjunction with other apparatus
- H04L25/03254—Operation with other circuitry for removing intersymbol interference
- H04L25/03267—Operation with other circuitry for removing intersymbol interference with decision feedback equalisers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
- H03K3/35613—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration
- H03K3/356139—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration with synchronous operation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L2025/03433—Arrangements for removing intersymbol interference characterised by equaliser structure
- H04L2025/03439—Fixed structures
- H04L2025/03445—Time domain
- H04L2025/03471—Tapped delay lines
- H04L2025/03484—Tapped delay lines time-recursive
- H04L2025/0349—Tapped delay lines time-recursive as a feedback filter
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- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Power Engineering (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Dc Digital Transmission (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Logic Circuits (AREA)
Description
で励起され、したがって、上部スライサ306は偶数データ・ビットDEを生成し、下部スライサ306は奇数データ・ビットDOを生成する。スライサ306の前にある加算器312は、DFEフィードバック信号を受信データ入力に加えるために使用される。第1のDFEフィードバック・タップ(H1)は、従来のディスクリート・タイプであり、チャネル・インパルス応答の第1のポストカーソルと一致するように独立して調整することができる。ハーフレート・アーキテクチャでは、前のデータ・ビットは反対側のDFEハーフによって判定され、したがって、偶数データ経路用のH1タップ(H1Eと示されている)は奇数データ・ビットからフィードバックされ、逆もまた同様である。チャネル・インパルス応答内のポストカーソルの残りによるISIは、IIRフィルタ304の出力であるVIIRによって補償される。
Claims (14)
- 1/nレート判定帰還型等化器(DFE)であって、
複数の分岐を含み、各分岐が、
受信入力にフィードバック信号を加えるように構成された加算器回路と、
クロック信号により前記加算器回路の出力を受け取るように構成されたラッチと、
フィードバック回路と、
を含み、前記フィードバック回路が、
各分岐の出力を入力として受け取るように構成されたマルチプレクサであって、クロック化選択入力を有し、各分岐の出力を多重化してフルレート・ビット・シーケンスをアセンブルするように構成されたマルチプレクサと、
各分岐の前記加算器回路に提供すべき前記受信入力から符号間干渉(ISI)を除去するために、前記マルチプレクサより供給される前記フルレート・ビット・シーケンスを濾波して前記フィードバック信号を出力する連続時間無限インパルス応答(IIR)フィルタを含むフィルタと、
を含む、1/nレート判定帰還型等化器(DFE)。 - 前記ラッチに結合された少なくとも1つの追加のラッチをさらに含み、各追加のラッチが、前記加算器回路にフィードバック・タップを提供して、前記受信入力に前記フィードバック・タップを加えるためのフィードバック・ループを有する、請求項1記載のDFE。
- 前記ラッチがスライサを含み、前記スライサが単一ステージで前記加算器回路と結合される、請求項1または2のいずれかに記載のDFE。
- 各分岐が、前記スライサおよび前記加算器回路を備えた前記単一ステージを含み、クロック・サイクルのフェーズ中にデータを有効に保持するために前記単一ステージの出力側に配置されたスレーブ・ラッチをさらに含む、請求項3記載のDFE。
- 前記スレーブ・ラッチがダブル再生ラッチを含む、請求項4記載のDFE。
- 前記マルチプレクサおよび前記フィルタが単一ステージで結合される、請求項1ないし5のいずれかに記載のDFE。
- 判定帰還等化のための方法であって、
複数の分岐を有する1/nレート判定帰還等化回路を設けることと、
加算器回路を使用して1つまたは複数の分岐からのフィードバック信号と受信入力とを合計することと、
クロック信号によりラッチで前記加算器回路の出力を受け取ることと、
各分岐の前記出力を入力として受け取るマルチプレクサであって、各分岐の前記出力を多重化してフルレート・ビット・シーケンスをアセンブルするように構成されたマルチプレクサに前記ラッチの前記出力をフィードバックすることと、
前記マルチプレクサより供給される前記フルレート・ビット・シーケンスを濾波して前記フィードバック信号を出力する連続時間無限インパルス応答(IIR)フィルタを使用して前記受信入力から符号間干渉(ISI)を除去すること、
を含む、方法。 - 前記加算器回路にフィードバック・タップを提供して、少なくとも1つの追加のラッチから前記受信入力に前記フィードバック・タップを加えることをさらに含む、請求項7記載の方法。
- 前記ラッチおよび前記加算器回路が単一ステージで結合され、ダブル再生ラッチを使用して前記単一ステージの出力を再生することをさらに含む、請求項7または8に記載の方法。
- 前記ダブル再生ラッチが、改善された速度と感度を達成するために2つのカスケード式差動再生ラッチ・ステージ(702、704)を含み、前記ステージが、
第1のタイプの第1の入力トランジスタ(706)と、第2のタイプのクロスカップル型ロード・トランジスタ(711)およびリセット・トランジスタとを有する第1のステージ(702)と、前記第2のタイプの第2の入力トランジスタ(708)と、前記第1のタイプのクロスカップル型ロード・トランジスタ(712)とを有する第2のステージ(704)とを含み、前記第1のステージが前記リセット・トランジスタによって前記第1のステージの出力が電源電圧にプレチャージされる不透明な状態になっているときに、前の保管ビットを示すレベルに出力を保持するために前記第2のステージの前記第2の入力トランジスタが遮断されるようになっており、前記第1のステージが活動化されると、前記第1のステージおよび前記第2のタイプの前記クロスカップル型ロード・トランジスタが入力信号を再生し始め、同時に、前記第1のステージの出力同相モードが低下して前記第2のステージの前記第2の入力トランジスタをオンにし、前記第2のステージが、前記第1のタイプの前記クロスカップル型ロード・トランジスタを含み、追加の再生利得を提供するために前記第1のステージの前記出力がしきい信号レベルを達成した後で切り替えられる、請求項5に記載のDFE。 - 前記ダブル再生ラッチが前記スライサから出力を受け取り、前記第1のステージと前記スライサが同時に再生するように前記スライサが再生している間に前記第1のステージが再生に入る、請求項10記載のDFE。
- 前記スライサと前記加算器回路とが結合した結合スライサ加算器回路を含み、前記結合スライサ加算器回路が、
合計すべき複数の差動電流に接続された差動出力線と、
前記差動出力線に直接結合されたリセット可能な電流比較器負荷であって、合計した差動電流の符号に応じて正または負の差動電圧が前記差動出力線の間に発生して2進の0または1をラッチするように、前記合計した差動電流を前記差動出力線から直接受け取るように構成されたリセット可能な電流比較器負荷と、
を含む、請求項3〜5、10、11のいずれか1項に記載のDFE。 - 前記差動電流が、線形トランスコンダクタによって生成された入力信号と、前記DFE内でフィードバックとして提供されるタップ信号およびフィルタ信号のうちの少なくとも1つとを含む、請求項12記載のDFE。
- 評価フェーズ中に前記線形トランスコンダクタへの前記入力信号を一定に保持するためにクロックにより切り替えられた前記入力信号を受け取るように前記線形トランスコンダクタに結合されたパスゲート・サンプルアンドホールド回路をさらに含む、請求項13記載のDFE。
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US12/366,843 | 2009-02-06 | ||
US12/366,843 US8477833B2 (en) | 2009-02-06 | 2009-02-06 | Circuits and methods for DFE with reduced area and power consumption |
PCT/EP2010/050286 WO2010089170A2 (en) | 2009-02-06 | 2010-01-12 | Circuits and methods for dfe with reduced area and power consumption |
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JP2012517170A JP2012517170A (ja) | 2012-07-26 |
JP5506825B2 true JP5506825B2 (ja) | 2014-05-28 |
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EP (1) | EP2389748B1 (ja) |
JP (1) | JP5506825B2 (ja) |
KR (1) | KR101539816B1 (ja) |
CN (1) | CN102301665B (ja) |
TW (1) | TWI467972B (ja) |
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Families Citing this family (63)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7869498B2 (en) * | 2006-09-14 | 2011-01-11 | Lsi Corporation | Low power decision feedback equalization (DFE) through applying DFE data to input data in a data latch |
US8401065B2 (en) * | 2011-02-14 | 2013-03-19 | Fujitsu Limited | Clock recovery circuit for receiver using decision feedback equalizer |
US8731041B2 (en) * | 2011-04-21 | 2014-05-20 | Stmicroelectronics (Canada) Inc. | Parallel closed-loop DFE filter architecture |
US8798484B2 (en) * | 2012-02-16 | 2014-08-05 | International Business Machines Corporation | Optical receiver using infinite impulse response decision feedback equalization |
US8737549B2 (en) * | 2012-04-30 | 2014-05-27 | Lsi Corporation | Receiver having limiter-enhanced data eye openings |
US8537886B1 (en) * | 2012-07-05 | 2013-09-17 | Altera Corporation | Reconfigurable equalization architecture for high-speed receivers |
CN102780663B (zh) * | 2012-07-09 | 2015-02-25 | 清华大学深圳研究生院 | 一种应用于高速串行接口的连续时间均衡电路 |
US8643422B1 (en) * | 2012-07-12 | 2014-02-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Slicer and method of operating the same |
US9106461B2 (en) * | 2012-07-20 | 2015-08-11 | Fujitsu Limited | Quarter-rate speculative decision feedback equalizer |
US9059874B2 (en) * | 2012-08-15 | 2015-06-16 | Marvell World Trade Ltd. | Switched continuous time linear equalizer with integrated sampler |
US8824540B2 (en) * | 2012-08-22 | 2014-09-02 | International Business Machines Corporation | Decision feedback equalizers with high-order continuous time feedback |
US8786365B2 (en) * | 2012-09-04 | 2014-07-22 | Nanya Technology Corporation | External programmable DFE strength |
US9094239B1 (en) * | 2012-10-01 | 2015-07-28 | Altera Corporation | Apparatus and method for polarity tap control |
US8929428B2 (en) * | 2012-10-30 | 2015-01-06 | International Business Machines Corporation | Feed-forward equalization in a receiver |
US9319248B2 (en) * | 2012-12-21 | 2016-04-19 | Nvidia Corporation | Decision feedback equalizer using current mode processing with CMOS compatible output level |
CN103229473B (zh) * | 2012-12-28 | 2015-04-08 | 华为技术有限公司 | 判决反馈均衡器和接收机 |
US8976855B2 (en) | 2013-03-14 | 2015-03-10 | Intel Corporation | Power and area efficient receiver equalization architecture with relaxed DFE timing constraint |
US9237045B2 (en) * | 2013-03-15 | 2016-01-12 | Avago Technologies General Ip (Singapore) Pte. Ltd. | System and method for internal AC coupling with active DC restore and adjustable high-pass filter for a PAM 2/4 receiver |
US9660624B1 (en) | 2014-03-21 | 2017-05-23 | Altera Corporation | Methods and apparatus for implementing feedback loops |
GB2525428A (en) | 2014-04-24 | 2015-10-28 | Ibm | Decision-Feedback Analyzer and methods for operating the same |
US9197458B1 (en) * | 2014-05-01 | 2015-11-24 | Samsung Display Co., Ltd. | Edge equalization via adjustment of unroll threshold for crossing slicer |
US9231793B1 (en) | 2014-05-19 | 2016-01-05 | Albert Vareljian | Full bridge decision feedback equalizer |
US9531570B2 (en) * | 2014-05-27 | 2016-12-27 | Samsung Display Co., Ltd | CML quarter-rate predictive feedback equalizer architecture |
US9680668B2 (en) * | 2014-12-16 | 2017-06-13 | Intel Corporation | Delay resilient decision feedback equalizer |
US9374250B1 (en) * | 2014-12-17 | 2016-06-21 | Intel Corporation | Wireline receiver circuitry having collaborative timing recovery |
US9397824B1 (en) * | 2015-01-28 | 2016-07-19 | Texas Instruments Incorporated | Gear shifting from binary phase detector to PAM phase detector in CDR architecture |
US10341145B2 (en) * | 2015-03-03 | 2019-07-02 | Intel Corporation | Low power high speed receiver with reduced decision feedback equalizer samplers |
US9882795B1 (en) * | 2015-04-17 | 2018-01-30 | Xilinx, Inc. | Signal loss detector |
US10431707B2 (en) | 2015-04-30 | 2019-10-01 | Hewlett Packard Enterprise Development Lp | Monolithically integrated photodetector and receiver |
US9628302B2 (en) | 2015-05-21 | 2017-04-18 | International Business Machines Corporation | Decision feedback equalizer |
US9660843B2 (en) * | 2015-06-05 | 2017-05-23 | Texas Instruments Incorporated | Apparatus for processing a serial data stream |
US9584306B2 (en) * | 2015-06-18 | 2017-02-28 | Altera Corporation | Phase detection in an analog clock data recovery circuit with decision feedback equalization |
US9699007B2 (en) * | 2015-08-31 | 2017-07-04 | Huawei Technologies Co., Ltd. | Pipeline multiplexer loop architecture for decision feedback equalizer circuits |
US9722828B2 (en) * | 2015-09-23 | 2017-08-01 | Qualcomm Incorporated | Switch capacitor decision feedback equalizer with internal charge summation |
US9595975B1 (en) | 2015-09-30 | 2017-03-14 | Samsung Display Co., Ltd. | Low-latency high-gain current-mode logic slicer |
CN105681238B (zh) | 2016-02-03 | 2018-11-09 | 晨星半导体股份有限公司 | 一种模拟均衡器 |
CN107220193B (zh) * | 2016-03-21 | 2019-06-11 | 综合器件技术公司 | 用于单端信号均衡的装置和方法 |
TWI617159B (zh) * | 2016-06-15 | 2018-03-01 | 晨星半導體股份有限公司 | 模擬等化器 |
EP3480962B1 (en) * | 2016-06-30 | 2021-04-07 | Socionext Inc. | Equalizing circuit, reception circuit, and semiconductor integrated circuit |
US9876656B1 (en) * | 2016-07-11 | 2018-01-23 | Xilinx, Inc. | Differential feedback equalizer and method of implementing a differential feedback equalizer |
US9860087B1 (en) | 2016-08-31 | 2018-01-02 | International Business Machines Corporation | Low power speculative decision feedback equalizer |
US10075308B2 (en) | 2016-09-30 | 2018-09-11 | Intel Corporation | Supply voltage adaptation via decision feedback equalizer |
US10187234B1 (en) * | 2017-11-13 | 2019-01-22 | Huawei Technologies Co., Ltd. | Decision feedback equalizers and methods of decision feedback equalization |
KR102636148B1 (ko) * | 2017-11-21 | 2024-02-14 | 삼성전자주식회사 | 신호 수신기의 동작 방법, 펄스 폭 제어기, 및 그것들을 포함하는 전자 장치 |
US10615778B2 (en) * | 2018-02-19 | 2020-04-07 | Analog Devices, Inc. | Crest factor reduction |
US10476707B2 (en) | 2018-03-05 | 2019-11-12 | Samsung Display Co., Ltd. | Hybrid half/quarter-rate DFE |
CN108964627B (zh) * | 2018-06-06 | 2022-03-15 | 杭州电子科技大学 | 针对屏蔽差分硅通孔的rc无源均衡器结构及其设计方法 |
JP2020048021A (ja) | 2018-09-18 | 2020-03-26 | キオクシア株式会社 | 等化回路及び受信機 |
US10904044B2 (en) * | 2019-01-31 | 2021-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Serdes receiver with optimized CDR pulse shaping |
TWI681651B (zh) | 2019-03-13 | 2020-01-01 | 瑞昱半導體股份有限公司 | 決策回授等化器 |
KR102203394B1 (ko) * | 2019-04-05 | 2021-01-15 | 고려대학교 산학협력단 | 4 레벨 펄스 진폭 변조 신호 기반의 판정 궤환 등화 회로 및 그 동작 방법 |
US10848353B1 (en) * | 2019-06-28 | 2020-11-24 | Intel Corporation | Multi-tap decision feedback equalizer (DFE) architecture with split-path summer circuits |
TWI722689B (zh) | 2019-11-29 | 2021-03-21 | 財團法人工業技術研究院 | 適用於偏移正交振幅調變濾波器組多載波空間多工系統之偵測器及干擾消除方法 |
US11212143B1 (en) | 2020-06-29 | 2021-12-28 | Huawei Technologies Co., Ltd. | Sliding block decision equalizer |
DE112021006023T5 (de) * | 2020-11-19 | 2023-09-07 | Microchip Technology Incorporated | Entscheidungsrückkopplungsabgriffsysteme und zugehörige einrichtungen und verfahren |
CN112714085B (zh) * | 2020-12-11 | 2022-06-28 | 硅谷数模(苏州)半导体有限公司 | 判决反馈均衡电路 |
US11870615B2 (en) | 2021-06-11 | 2024-01-09 | Samsung Electronics Co., Ltd. | Summing circuit and equalizer including the same |
US11973623B2 (en) | 2021-06-11 | 2024-04-30 | Samsung Electronics Co., Ltd. | Latch circuit and equalizer including the same |
US11729029B2 (en) | 2021-08-31 | 2023-08-15 | Analog Bits Inc. | Method and apparatus for low latency charge coupled decision feedback equalization |
US11973621B2 (en) | 2021-12-17 | 2024-04-30 | Samsung Display Co., Ltd. | Power efficient slicer for decision feedback equalizer |
JP2023139897A (ja) * | 2022-03-22 | 2023-10-04 | キオクシア株式会社 | 受信装置および受信方法 |
US11770274B1 (en) | 2022-05-24 | 2023-09-26 | Apple Inc. | Receiver with half-rate sampler circuits |
KR20240036276A (ko) | 2022-09-13 | 2024-03-20 | 고려대학교 산학협력단 | 시간 도메인에서 반사 신호를 효과적으로 제거하는 수신기 |
Family Cites Families (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0330528A (ja) * | 1989-06-28 | 1991-02-08 | Hitachi Ltd | 等化器及びその性能評価方法 |
US5031194A (en) * | 1989-08-11 | 1991-07-09 | Bell Communications Research, Inc. | Wideband digital equalizers for subscriber loops |
US5134319A (en) | 1990-01-10 | 1992-07-28 | Fujitsu Limited | Bicmos differential amplifier having improved switching speed |
US5293402A (en) | 1991-05-02 | 1994-03-08 | Bell Communications Research, Inc. | Wideband digital equalizers for subscriber loops |
US5491653A (en) * | 1994-10-06 | 1996-02-13 | International Business Machines Corporation | Differential carry-save adder and multiplier |
US6115418A (en) | 1998-02-09 | 2000-09-05 | National Semiconductor Corporation | Simplified equalizer for twisted pair channel |
US6724844B1 (en) * | 1998-06-30 | 2004-04-20 | Koninklijke Philips Electronics N.V. | Method and device for improving DFE performance in a trellis-coded system |
CN1060300C (zh) | 1998-09-11 | 2001-01-03 | 国家科学技术委员会高技术研究发展中心 | 选取抽头系数的判决反馈均衡器 |
US7006565B1 (en) | 1999-04-15 | 2006-02-28 | Ati Technologies Inc. | Hybrid soft and hard decision feedback equalizer |
US6137319A (en) * | 1999-04-30 | 2000-10-24 | Intel Corporation | Reference-free single ended clocked sense amplifier circuit |
GB2349996A (en) | 1999-05-12 | 2000-11-15 | Sharp Kk | Voltage level converter for an active matrix LCD |
KR100772850B1 (ko) * | 1999-12-24 | 2007-11-02 | 코닌클리케 필립스 일렉트로닉스 엔.브이. | 데이터 수신기에서의 소거 기반 순시 루프 제어 |
US6757909B1 (en) | 1999-12-29 | 2004-06-29 | Sony Corporation | Internet set-top box having an in-band tuner and cable modem |
US6751255B1 (en) * | 2000-03-09 | 2004-06-15 | Orckit Communications, Ltd. | Decision feedback analyzer with filter compensation |
US7027500B1 (en) * | 2000-12-12 | 2006-04-11 | Ati Research, Inc. | Linear prediction based initialization of a single-axis blind equalizer for VSB signals |
US6856649B2 (en) * | 2001-03-30 | 2005-02-15 | Koninklijke Philips Electronics N.V. | Initialization scheme for a hybrid frequency-time domain equalizer |
US6580294B1 (en) * | 2001-12-18 | 2003-06-17 | Intel Corporation | Zipper domino carry generate cell for fast adders |
KR100916377B1 (ko) * | 2002-04-16 | 2009-09-07 | 톰슨 라이센싱 | 결정 피드백 등화기 및 결정 피드백 등화를 위한 방법 |
US20040027185A1 (en) | 2002-08-09 | 2004-02-12 | Alan Fiedler | High-speed differential sampling flip-flop |
JP3764135B2 (ja) | 2002-10-31 | 2006-04-05 | Necエレクトロニクス株式会社 | レベルシフタ |
US7346105B2 (en) | 2003-04-25 | 2008-03-18 | Dotcast, Inc. | Decision feedback equalization with fractionally-spaced feedback data |
US7889786B2 (en) * | 2003-08-29 | 2011-02-15 | Diablo Technologies Inc. | Operating frequency reduction for transversal FIR filter |
US20050232347A1 (en) | 2004-04-15 | 2005-10-20 | Mediatek Incorporation | Apparatus and method for noise enhancement reduction in an adaptive equalizer |
US7177352B1 (en) * | 2004-05-28 | 2007-02-13 | Pmc-Sierra, Inc. | Pre-cursor inter-symbol interference cancellation |
KR100698630B1 (ko) | 2004-06-28 | 2007-03-21 | 삼성전자주식회사 | 스텝사이즈 조정기능을 구비한 등화기 및 등화방법 |
US7106099B1 (en) | 2004-10-22 | 2006-09-12 | Xilinx, Inc. | Decision-feedback equalization clocking apparatus and method |
KR100640591B1 (ko) | 2004-10-23 | 2006-11-01 | 삼성전자주식회사 | 감소된 면적을 가지는 부분 탭 적응 등화기 |
WO2006078845A2 (en) * | 2005-01-20 | 2006-07-27 | Rambus Inc. | High-speed signaling systems with adaptable pre-emphasis and equalization |
US7542508B2 (en) * | 2005-04-21 | 2009-06-02 | Lsi Logic Corporation | Continuous-time decision feedback equalizer |
JP2006332731A (ja) * | 2005-05-23 | 2006-12-07 | Nagasaki Institute Of Applied Science | Cmosラッチ式コンパレータ |
US7800411B1 (en) * | 2006-01-30 | 2010-09-21 | National Semiconductor Corporation | System and method for providing a strobed comparator with reduced offset and reduced charge kickback |
US7358790B2 (en) | 2006-02-17 | 2008-04-15 | Himax Technologies Limited | High performance level shift circuit with low input voltage |
US7362153B2 (en) * | 2006-05-01 | 2008-04-22 | Intel Corporation | Receiver latch circuit and method |
US7782935B1 (en) * | 2006-08-31 | 2010-08-24 | Altera Corporation | Half-rate DFE with duplicate path for high data-rate operation |
US7715474B2 (en) * | 2007-02-07 | 2010-05-11 | International Business Machines Corporation | Decision feedback equalizer (DFE) architecture |
US7822114B2 (en) * | 2007-06-12 | 2010-10-26 | International Business Machines Corporation | Decision feedback equalizer using soft decisions |
US20080310485A1 (en) | 2007-06-15 | 2008-12-18 | Qualcomm Incorporated | System and methods for controlling modem hardware |
US7936812B2 (en) * | 2007-07-02 | 2011-05-03 | Micron Technology, Inc. | Fractional-rate decision feedback equalization useful in a data transmission system |
JP4956840B2 (ja) * | 2008-03-14 | 2012-06-20 | 日本電気株式会社 | 判定帰還等化装置及び方法 |
JP5400567B2 (ja) | 2009-10-23 | 2014-01-29 | 株式会社東芝 | 半導体スイッチ |
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Also Published As
Publication number | Publication date |
---|---|
EP2389748B1 (en) | 2017-08-09 |
US20130287089A1 (en) | 2013-10-31 |
US9444437B2 (en) | 2016-09-13 |
US8477833B2 (en) | 2013-07-02 |
JP2012517170A (ja) | 2012-07-26 |
KR101539816B1 (ko) | 2015-07-27 |
US20150256160A1 (en) | 2015-09-10 |
TWI467972B (zh) | 2015-01-01 |
US20100202506A1 (en) | 2010-08-12 |
KR20110129389A (ko) | 2011-12-01 |
US9008169B2 (en) | 2015-04-14 |
EP2389748A2 (en) | 2011-11-30 |
CN102301665A (zh) | 2011-12-28 |
TW201136248A (en) | 2011-10-16 |
WO2010089170A3 (en) | 2011-04-14 |
WO2010089170A2 (en) | 2010-08-12 |
US20120314757A1 (en) | 2012-12-13 |
CN102301665B (zh) | 2015-02-25 |
US9806699B2 (en) | 2017-10-31 |
US20150200792A1 (en) | 2015-07-16 |
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