TW201136248A - Circuits and methods for DFE with reduced area and power consumption - Google Patents

Abstract

A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a summer circuit configured to add a feedback signal to a received input, and a latch configured to receive an output of the summer circuit in accordance with a clock signal. A feedback circuit includes a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence, and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input to be provided to the summer circuit of each branch.

Description

201136248 VI. OBJECTS OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention generally relates to equalization techniques for high speed data, and more particularly to implementation of decision feedback equalizer circuits, and high speed data communication with improved power efficiency. method. [Prior Art] When the processing power of the digital computing engine grows with the improvement of technology, and the network of the daily surplus interconnect is developed to use this capability, systems such as servers and data communication channels require higher bandwidth. Data transmission. Since the bandwidth of the channel is limited, it is difficult to increase the serial link data rate to a few gigabns per second. The bandwidth of an electrical channel (such as a transmission line) is reduced by many physical effects, including surface effects, dielectric losses, and reflections caused by unsteady impedance. In terms of time, the limited channel bandwidth causes the transmission to exceed one unit interval (Unitinterval, and the received L-symbol interference (Intersymb〇i jnterference, isis) 〇 one to compensate for the finite channel bandwidth The effective method of signal distortion is to add equalization function in the wheel input/output (I/O) circuit. Use the feedback feedback equalizer in the receiver (Decisi〇n_feedback eqUaHzer, 'made for silk and other high loss Channel. For linear equalizers, DFE flattens the channel response (and reduces the distortion of the ^). It does not amplify noise or crosstalk, which is a key advantage in channel loss over 20-30 dB. Read Figure 丨, which illustrates the conventional multi-tap DFE 10. In the displacement temporary delay line formed by a series of 201136248 string latches 14, the binary output of the limiter (or latch) 12 is determined. The previous decision bits stored in the device (14) are fed back with weighted tap coefficients (HI, H2, ..., HN) and added to the received input signal using a summing amplifier (or adder) 16. Weight (HI, H2, etc.) The amplitude and polarity are properly adjusted to match the channel characteristics, which will eliminate the ISI from the data stream (called the "post-marker ISI (ISI))" and use the limited field device 12 The bit error rate (BER) is used to detect the bit. The adjustment of the tap weight can be manually performed by an appropriate adaptive algorithm. In general, the more taps are supplied to eliminate the ISI, The greater the effect of equalization, the actual DFE implementation usually uses up to 1 feedback taps to achieve the difference in the data rate of several gigabits per second for different electrical channels. Unfortunately, multiple taps make a large number of (4) The _ and anti-chapter circuits consume large recording power and wafer area. In some lie there are thousands of 1/0 high-end processing twins. ί 'Traditional multi-tap DFE = ^ area cost is very high' because The I/O circuit consumes most of the system's power and area budget. The area and power requirements of the digital technology are high-density, fine-pitched, and the chip is interconnected to the chip. The example of the species is the Shi Xi carrier, which is depicted in Figure 2. The basic concept. ητ 〇月麦看图2, two wafers 20 and 22 are fixed to the 矽 carrier 24 # Β 2 wiring 26 is connected to i. This surface wiring 26 is close (to make S 'M〇S back-end process (Back-end -of-line, BE0L) treatment only ^ 201136248 microns, allowing the formation of high density columns between wafers 2G and 22. The stone penetration holes 28 are used to vertically connect the power between the wafer 2 () and the 22 array package And the signal. Since the surface line 26 of the first body is connected with a significant unit length per unit length, the 1/n rate decision feedback equalizer (DFE) includes a plurality of branches and branches. The include-adder circuit is configured to receive a wire-feedback signal to the received input y and the -lock lock, configured to receive an output of the adder circuit in accordance with the clock signal. A feedback circuit includes: a multiplexer configured to receive an output of each branch as an input, the multiplexer having two clock selects A and configured to convert the output of each branch to a full rate bit a sequence of elements; and a filter configured to cancel inter-symbol interference (ISI) from among the received inputs of the adder circuit to be provided to each branch. A method for decision feedback equalization, comprising: providing a 1/n rate decision feedback equalization circuit with a plurality of knives; using a sigma circuit to feedback a feedback signal from one or more branches Receiving an input sum; receiving a output of the adder circuit using a latch according to a clock signal; feeding an output of the latch to a multiplexer that receives the output of each branch as an input, The multiplexer is configured to combine the output of each branch to combine a full rate bit sequence; and use a continuous time infinite impulse response (IRR) chopper having a frequency domain conversion function, Elimination of Inter-Interference (1SI) from the received input 〇 201136248 A combined limiter and adder circuit includes a differential wheel outlet connected to a plurality of differential currents to be summed. A resettable current comparator load is directly coupled to the differential output line, the current comparator load configured to directly receive the summed differential current from the differential output line such that the differential current is summed according to the A sign that produces a positive or negative differential voltage between the differential output lines to lock a binary zero or one. The dual regenerative latch includes two serially connected differential regenerative latch stages for improved speed and sensitivity. The stage includes a first stage having a first type of first-transistor transistor, a load-and-light load cell & and a first type of reset transistor, and a second stage, The second input transistor having the second type and the intersection of the first type cause the first stage to be in a non-transmissive state, and the output of the reset transistor stage is precharged to the power supply voltage. The second stage of: the break-in transistor is turned off to maintain the output at the level indicating the previous storage level ^. After the first stage is started, the first stage and the = again: the combined load transistor starts to regenerate an input signal, the second = the common mode drop, the second stage of the second stage is turned on, and the first side of the second stage The present invention provides a decision feedback equalizer (DFE) circuit and method, and its method is used in 201136248, and the wave II is replaced in the noodle circuit. Multiple feedback loops used in ISI. In a particular embodiment, the 1/n rate view (e.g., abundance rate, quarter rate, etc.) includes an infinite impulse response __'11 Congler, which acts as a feedback apostrophe for the summing amplifier. In addition, a combined summing limiter circuit is provided to further reduce the area and power consumption. A dual regenerative latch is also available. The specific embodiment of the present invention may adopt the specific implementation of the entire hardware embodiment, the entire software, or the specific implementation of the component. In a preferred embodiment, the invention is practiced in a soft body, which is not limited to firmware, retention software, microcode, and the like. Furthermore, the present invention can be in the form of a computer program product that can be accessed from a computer or computer readable ship, providing code for use or connection to a computer or any instruction execution system. For the sake of illustration, any device that can be read, stored, communicated, transmitted, or transmitted by a computer or computer can be used to connect or connect devices. The medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or device or device). Examples of computer readable media include semiconductor or solid state memory, magnetic tape, removable computer magnetic disk, random access memory (RAM), read only memory (Read_〇nly ^emoiy^ROM ), hard drive and CD. Currently, examples of optical discs include "Compact disc read-only memory (CD-ROM), rewritable disc (CD-R/W), and DVD. A data processing system suitable for storing and/or executing code may include at least one process coupled directly or indirectly through a system bus to a memory component|§. The memory component can include the real P-execution code used by the p i- -* ] 8 201136248 The storage and the provision of at least some of the code temporary storage reduction during execution must be taken from a large amount of storage = rounded / Output or 1/0 device (including but not word-to-day shock, etc.) can directly or through the money 1/0 control light card is also integrated into the system, let the (4) processing system become 5 data processing system 'or Coupling or staggering devices through intermediate private or public networks. Data machines, cable modems, and Ethernet cards, and some of the currently available types of network adapters. The circuit described herein can be a design of integrated circuit chips. The chip design can be set up in a hard-to-use language, and (10) exists, storing media as a towel (such as W, tape L (four) or like a storage access network (10) virtual hard disk). If you design 晶片 to manufacture a wafer or use a photolithographic mask to make crystals; ^ 'Designer materials (such as using the storage design _ storage (4)) or electronic materials (such as through the Internet) to design the results directly or Indirectly transmitted to such entities. The stored design is then converted to an appropriate format (e.g., gdsii) to create a photolithographic mask, which typically includes a number of copies of the wafer design to be formed on the wafer. A photolithographic mask is used to define the area of the circle (and/or layers thereon) to be etched or to be processed. Manufacturers can use the raw material wafer form (that is, as a single-crystal® with multiple unsealed I wafers), bare die or packaged form to produce the resulting circuit chip. In the latter case, the wafer is mounted in a single-chip package (such as a plastic carrier with wires attached to the motherboard or other higher-level carrier) or fixed in a multi-chip package (like one or both surfaces with surface interconnects^ 1 } 9 201136248 or embedded interconnected ceramic carrier). In any case, the wafer is integrated with other wafers, discrete circuit components, and/or other signal processing devices as part of an intermediate product or end product such as a machine board. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to incoming computer products with displays, keyboards or other input devices and central processing units. 3A and 3B, wherein the same reference numerals represent the same or similar elements, respectively showing the frequency domain (i.e., the S21 parameter) and the channel response of the 2 mm long link in the time domain, for the carrier link 26 of FIG. There is a significant (~6 dB) DC attenuation due to series resistance, and the loss at 5 GHz is 17 dB. In the time domain, the response to a single 」" bit on 1 〇gigabits per second shows a post-mark ISI that exceeds many bit periods. To complement this channel, DFE requires many taps, but the power and area costs associated with this high-density environment are impractical.

A careful study of time domain channel response has suggested an innovative solution to equalize this high impedance channel. The impulse response of the channel is modeled using a decay index over all time intervals of more than 2 unit intervals (UI) after the main marker. Since the impulse response of the first-order RC low-pass filter has a decaying exponent, the DFE feedback path (4) can be used to generate the desired filter to eliminate the ISI after the received data input. For example, a DFE with a first-order RC low-pass feedback chopper boosts the data rate of the interconnect on a 1-picture wafer to 2 per second. Because the traditional DFE actually needs a large number of taps that have been replaced by simple RC choppers, thus saving a lot of power and area. The tea has a continuous time infinite impulse response (IRIR) filter 104 having a frequency domain transfer function G(s) in the DFE feedback path | 〇 8(3) 201136248 of the dFE circuit. The summing amplifier 106 sums the feedback from the path 108 with the data input. When the channel response cannot approximate the first-order RC low-pass filter, a higher-order filter and waver are provided to better eliminate ISI°. See Figure 5 for many channels, if conventional discrete taps (such as H1, H2) and The IIR filter 204 is located within the feedback path 208 of the DFE 200, and even better ISI cancellation can be achieved. The first coupling of discrete taps (eg, H1 and H2) can be adjusted (independent of nR filter 204) to compensate for the mark immediately after the fast change region of the channel impulse response after the main marker because of these early post-marks and It does not fall within the exponential decay curve followed by the mark. In fact, the impulse response of the 20 mm 矽 carrier channel shown in Figure 3B illustrates this point 'because the first post-label (labeled H1) does not indeed fall within the curve labeled H2e_t/T' where 7 is the decay index Time constant. Therefore, the true equalization of the tantalum carrier link can utilize a DFE 200 with discrete taps (H1) that can be adjusted independently of the IIR filter 204 to compensate for the remaining post-marks in the channel response. Although DFE 2(8) with HR filter 204 is used to equalize the area and power efficiency structure of many channels, including the example 矽 carrier connection of Figure 2, the full rate DFE architecture is not suitable for extending this concept to higher data rates. The half-rate DEE architecture is more power efficient than the full-rate architecture in terms of data rates close to technical limits (such as 1 gigabits per second in current CM〇S technology). Since there is no full rate regenerative signal that can be used to drive the input of the 丨IR filter, the implementation of a half rate DFE with a 丨iR filter is extremely difficult. 201136248 Referring to Figure 6, a half rate dfe 3 (8) is shown in accordance with an illustrative embodiment. The half-rate DFE 3GG normally demultiplexes the input data into two parallel lean streams 302 (especially the even data bit % and the odd data bit call. Feeds a half rate data stream to the IIR filter 3〇) 4, does not give the desired response, because the correct ISI cancellation required for the impulse response of the IIR filter 3〇4 requires a complete sequence of bits, not just even data bits or odd data bits. As mentioned, in actual implementation In terms of half rate, it is a challenge to obtain an input suitable for driving the nR filter 304. The half rate architecture provides a power and area efficiency approach to obtain this signal. Using a pair of limiters driven by a half rate clock CLK (or latch) 306 to sample data input. Limiter 3〇6 is driven on the relative phase of CLK (eg, clk and όϊΖ) so that top limiter 3〇6 generates even data bit DE' and the bottom end The limiter 306 generates an odd data bit d. The DFE feedback signal is added to the received data input using the adder 312 before the limiter 306. The first DFE feedback tap (H1) is a conventional discrete type. And can be independently adjusted to respond to channel impulses After a tag match, in the half rate architecture, the previous data bit is determined by the relative half DFE, so the H1 tap (labeled h1e) of the even data path is fed back from the odd data bit, and vice versa. The ISI generated by the remaining post-marker in the impulse response is compensated by the output of Viir', which is the output of the IIR filter 304. Correctly eliminating ISI requires the impulse response convolution of the IIR filter 304 (concolve) complete data rounding bit sequence To achieve this, a 2:1 multiplexer (MUX) 310 with a CLK-driven selector is used to interleave the even and odd data bits (DE* D〇) to form a full rate suitable for driving the input of the I1R filter 304. Data (dfr) 201136248 In the timing diagram of Figure 7, the phase of the CLK is adjusted using the Clock-and-data recovery 'CDR circuit or some other mechanism' to sample the input data bits in the center. Selecting the phase of the CLK signal that drives the MUX selection causes the DFRS to be delayed by one UI relative to the first arrival of the ϋΕ and D〇 bits, as shown in Figure 7. Because of this one UI delay, the IIR filter output (VIIR) The earliest The latter is labeled as the second (corresponding to the H2 tap in the conventional multi-drop DFE). The specific embodiment of Figure 6 represents the area and power efficiency of adding the IIR filter 3〇4 to the half rate DFE structure, The only circuit burden (except of course the IIR filter 304 itself) is the 2.1 MUX 310 used to form the full rate data. If the 2:1 MUX 310 and IIR filter 304 functions are combined in a single circuit, this small burden is negligible. Referring to Figure 8, a schematic diagram of an exemplary circuit implementation of a 2:1 MUX 410 and IIR tear wave 404 combined in a single current mode logic (CML) stage 400 is shown. Circuit 4 is fully differential, such that its differential output amplitude is proportional to the ID', which is the difference between the two tail current sources 406 and 408. Both the common-mode current (ICM) and the resistance rcm are set so that the desired common mode output level from the IIR filter 404 is available. Although the ID can be used to scale the amplitude of the differential output signal, the RC time constant of the IIR filter 404 can be adjusted by adjusting the impedance RD and the capacitance CD (e.g., switching resistance and switching capacitance). It should be noted that in the MUX/IIR filter circuit 400 incorporated herein, the only signal representing the full rate data is the net current delivered to the RC load. The summing amplifier 312 and limiter 306 within the architecture of Figure 6 can be implemented using conventional circuit techniques. According to an example, Figure 9 illustrates how these components are implemented. 201136248 becomes a CML circuit. Referring to Figure 9, signal summation is achieved in the current domain by connecting the dipoles of a plurality of transistor differential pairs (or collectors if implemented in a bipolar technique) together (dummy lines). The differential input (DIN) of the receive IIR filter and the differential of the output are resistively degenerated using resistor 452, allowing the voltage to be more linearly converted into current. Among other differential pairs used as the current switch 454, resistive attenuation is not used. The data inputs (Din and 5^) have a resistance r η connected to the voltage VteRM as an impedance termination. The tail current of the differential pair switched by the DFE feedback signal HI is adjusted to set the desired tap weight to compensate for the first post marker of isi. The differential pair of v〇s switching is used to provide DC current to compensate for static offset due to device mismatch. The summing current is converted into a voltage by the load resistor ru. The output voltage (heart and $) of the adder 456 is sampled by a limiter 458, which is implemented herein as a standard CML latch. Serializing the DFE summing amplifier 456 and limiter 458 as shown in Figure 9 is a conventional implementation, but has the disadvantage of adding significant delays to the critical path 460 in the DFE unless a significant amount of power is consumed. To achieve a reliable operation, the DFE feedback signal must be accurately established on the limiter input before making the next data decision. As indicated by the dashed line in Figure 9, the critical path 460 of dfe is the H1 feedback loop whose delay must be less than 1 UI. By reducing the settling time of the feedback signal, the RC time length on the output of the amplifier 456 can be added to this critical path 46〇 with a significant delay. To reduce the v RC day-to-day constant to meet the critical time requirement, the load impedance RL1 must often be reduced to a low value. To meet the amplifier gain and voltage swing requirements, 'the operating current must be increased proportionally to achieve a reduction in rl|, resulting in higher power consumption. The input stage of the data slicer 458 includes an impedance load R|2. I S] 14 201136248

Referring to Figure 1, a schematic diagram of a limiter and adder combination circuit 500 in accordance with one embodiment is shown. A higher power benefit approach that meets critical time requirements is to eliminate the Rc delay by directly injecting the total output current into the tunable PMOS load as a limiter 5〇2. When CLK is south and its complement is low, pM〇s resets the transistor and outputs the node to the positive supply. When CLK is low (and its complement is high), the sum of the parasitic capacitances on (4) is discharged to a low voltage. According to the sign of the summed differential current, when the JL or negative differential voltage is started to develop, the common mode is sufficiently low, the P-electrode f in the limiter 502 is turned on and provides a regenerative gain, thereby locking the binary zero or the voltage. polarity). Eliminating the rc between the summing and (10) functions is in line with the time limit of the DFE critical path, so that 5 Ray ιί you; I € to achieve the desired data rate. Combining these functions into a single circuit level also saves wafer area. d if into some schematic details to prove dfe performance 'eg: receiving with 1N level: ancient; 1 and channel gate sampling by CLK is switched and maintained 508, over _ level human to linear inductor constant, which is dependent on small input frequency Loss of this input signal maintains a reduced resistive decay of the receiver. The CML summing amplifier 'in the line 9' is converted to a linearity of current using the power υΙΝ and v丨丨R. The rate frame i makes the half speed path 500 of the D_G of 6G4. Because "he has a combination of the totalizer / limiter power to maintain effective _ ^ ^ total 眺 (four) secret will not place the secondary gate during the reset period = in the adder / limiter circuit 50〇 The output is valid. Although every two phases of r=CLK are maintained during the two phases... The 1st lock 602 is in a non-transparent (or closed) state, 201136248 and its corresponding adder/limiter circuit is heavy. Let's switch to the transparent (or open) state when evaluating its corresponding summed ji/limiter circuit 500. Therefore, the human latch 602 only adds less propagation delay to the 〇E and D〇 data outputs. It is understood that the specific embodiment illustrated in FIG. 1 is suitable for multi-drop DFE and dfe with IIR filter, in other words, the combination of the adder and the limiter is independent of whether or not the IIR filter is used in the DFE. For example: if utilized The differential current switch controlled by the DFE feedback signal H2 (and similarly displayed til) replaces the differential pair of the output of the receive IIR filter 604 (Viir) to obtain a combined summation suitable for use in a conventional dual tap DFE. / limiter circuit (500). If you want to have more than two tapped DFE, you can use More differential pair current adder 504 is added to modify the combined adder/limiter 500. The application of the combined adder/limiter circuit 5〇〇 can be used to achieve a useful use for reducing power and area. Knowing that the DFE is tapped, and the rc delay between the summing and locking functions is eliminated, making it easier to meet the critical time limit of any DFE. The multi-standard flash lock design can be used to implement the secondary flash lock shown in Figure 11. 602, including CML and static CMOS. However, these standard latches have shortcomings in application, such as: CML latches are generally considered the fastest available type, but their design of high static power and power efficiency DFE The goal is inconsistent, which is one of the motivations behind considering DFE with IIR filter. Static CMOS latch is more power efficient, but its lower speed will increase the critical path delay, thus reducing the maximum operating frequency of DFE. Referring to Figure 2, there is shown a schematic diagram of a latch structure 700 having differential regenerative stages 702 and 7〇4, which achieves an exemplary embodiment shown in Figure 12 than a static CMOS latch 16 201136248 =:1 os device 7〇6, and the second stage output will be complemented to low), so the output of the -OS switch 702(4)+/5 is precharged to the positive power supply. Because the first stage == on the power supply 'So close the pM〇s of the second level 7〇4' so this level maintains its output at the indication that the previous bit carries two ^: two ^ and its complement is high and wide because the negative parent fork is lighter' so the first Stage 7〇2 is turned on to start regenerating the input signal. At the same time, enter the output common mode of the first stage, and then turn on the input transistor of the second stage 704. The output of the first stage 7〇2 is regenerated to a sufficiently high level' Switch the logic state of the class. Because this stage 704 (unreceived clock signal) has a 又OS 712 in its load, additional regeneration is used to amplify its output. Once the regeneration is complete and the switching is completed, conduction through the series of transistor ceases, such that the latch consumes only dynamic power non-static power. For this reason, the latch is more power efficient than the CM L latch. In one embodiment, the latch 7 is particularly useful when receiving weak regeneration signals from components such as the adder/limiter (500 in the figure). In a particularly useful embodiment, the first stage 7〇2 of the latch 700 is regenerated at the same time as the previous assembly (e.g., the adder/limiter 5〇〇), such that the first stage 702 further amplifies the weak regeneration. input signal. The analog latch 7 结合 is combined with the adder/limiter 500 to confirm this advantage. The input signal to the adder/limiter 500 in the simulation is very small, so that only its output is weakly reproduced. The regeneration of the first stage 7〇2 is used to amplify the weak regenerative input signal of the f 201136248 to the lock H, but the non-synchronous clock becomes a high state (and its complement is low) to fully regenerate to the rail pair signal level. Due to the extra ±, the second stage 704 ❾ output is further amplified and is close to the rail to rail level. The second _ these ligaments (four) on the semi-supply electricity > 1 # common mode interlaced with each other 'making it suitable for S-drive drive still differential current switch (such as to achieve the opening of the sub-connection in Figure 9 and Figure 10 As well as any CML or CMOS logic circuit, we should understand that the dual regenerative latch illustrated in Figure 12 is suitable for DFE and systems other than DFE with IIR filter. As shown in Figure 4-1, the conventional multi-drop DFE contains A large number of latches, and the delay of these latches is a delay for each critical time path within the DFE, due to the superior speed and speed compared to other power efficiency latches (like static CM〇s latches) Sensitivity, dual regenerative latches 7 can be incorporated into conventional dfe architectures or other circuitry to enhance operating frequency without increasing power consumption. Furthermore, the bio-latch 700 can be used for many digital and mixed-signal systems. Basic construction, block 2 because the speed and sensitivity of the latch usually have a large impact on the overall system b, many of these systems benefit from the superior functionality of the dual regenerative latch 7 (8). Half rate DF of IIR filter The functionality of E and the evaluation of its performance, the design and manufacture of test wafers using 65 nm bulk CMOS technology. Since the combined adder/limiter '5〇〇 of Figure 10 has been used, Figure 11 shows the selection. For the specific DFE architecture designed, as shown in Figure 8 '2:1 MUX and 1IR; the filter is combined in a single stage 4〇〇, and the secondary latch is implemented as the dual regenerative latch 30^ of Figure 12. 4, >ϋ;;; 枓, to test the equalization power of DFE with 丨丨R filter, these lines 201136248 have similar smoothing frequency attenuation (r 〇11 〇 ff) characteristics expected in the 矽 carrier link. The frequency response of these channels is shown in Figure 13. The bathtub curve in the right half of the figure shows that bER is a function of the clock sampling position when the PRBS7 data is equalized by 10 gigabits per second in accordance with DFE. For the 50" line, the DFE with the IIR filter has a 45% horizontal aperture at T9 and no error operation in the center of the aperture, thus consuming only 6.8 mW of power. In contrast, using and having The same basic components and power consumption levels of the DFE of the IIR filter The implementation of the conventional double is connected to the DFE. Table 1 is for the prbS7 and PRBS31 t material patterns at a lOgigabits per second data rate, comparing the measurement horizontal opening with the HR filter, the wave device ❹FE and the conventional double tap DFE opening. On the test channel, the DFE with the IIR filter surpasses the double tap dfe in performance, highlighting the effects of the present invention.

Table 1 Apricot flat opening (BER<〗 xirr> 2 tap DFE

ί 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解 了解The preferred embodiment of the circuit and method of the DFE is exemplified (and is not intended to be limiting). It is noted that modifications and variations can be made by those skilled in the art after the above description. Therefore, it is to be understood that the specific embodiments disclosed herein may be modified within the scope and spirit of the invention as set forth in the appended claims. The parts claimed and protected by the patent law will be disclosed in the scope of the appended claims after the details of the invention and the specific requirements. BRIEF DESCRIPTION OF THE DRAWINGS In the description of the preferred embodiments with reference to the following drawings, a more detailed description of the disclosed items will be provided, wherein: Figure 1 shows the tap weights with the adjustments to match the channel response marks. A conventional block diagram of multiple tapping DFE; view FIG. 2 is a cross-sectional view of the carrier-connected two-wafer-$carrier and the image of the carrier channel of Figure 3B and Figure 3B. Its upper time 4 does not S21 respond to the upper frequency and Figure 3B shows the impulse response

Chopping = There is an analogy of the continuous time in the IIR service with a conventional discrete tap and one = the use of the 丨丨 domain wave 11 represents - a block diagram of the specific embodiment of the odds architecture; Figure 7 is used for the figure Timing diagram of the half-rate DFE architecture shown in Figure 6; I S3 20 201136248 Figure 8 is a schematic diagram showing an example circuit implementation in which a -2: ΐΜυχ and filter are combined in a single stage; Additive Amplifier ~ Figure 10 is a diagram showing a DFE and a limiter combination to a single-stage according to one embodiment; ^Additional Figure 11 shows the use of a IIIU filter to represent a transfer ω δ adder Block diagram of a half-rate architecture for a limited-n-circuit circuit; Figure 12 is a schematic diagram showing a dual regenerative latch in accordance with one embodiment; and Figure 13 shows a 30" '40' and 50" PCB channel Frequency response, and the use of a half-rate DFE equalization with an IIR filter according to the present principle; then the BER must be a bathtub curve. [Major component symbol description] 10 Decision feedback equalizer 12 Limiter 14 Latch Locker 16 adder 20 wafer 22 wafer 24矽 carrier 26 surface wiring 26 carrier connection 28 矽 penetration hole 100 DFE circuit 104 infinite impulse response filter 201136248 106 total amplifier 108 path 200 decision feedback equalizer 204 IIR filter 208 feedback path 300 half rate DFE 302 data stream 304 IIR Filter 306 Limiter 312 Adder 310 Multiplexer 400 Single Current Mode Logic (CML) Stage 400 MUX/IIR Filter Circuit 404 IIR Filter 406 Tail Power Supply 408 Tail Power Supply 410 Multiplexer 452 Resistor 454 Current Switcher 456 Adder 458 Limiter 460 Critical Path 500 Combined Limiter and Adder Circuitry 502 Limiter 506 PMOS Reset Transistor 504 Current Adder 507 PMOS Transistor 508 Channel Gate Sampling Maintenance 22 201136248 600 604 602 700 702 704 706 708 711 710 712 Decision feedback equalizer IIR filter secondary latch latch structure differential regenerative stage differential regenerative stage NMOS device PMOS device PMOS transistor PMOS switch NMOS transistor m twenty three

Claims (1)

201136248 VII, the scope of application for patents: L - kind of speed surface anti-fresh H (DFE), which includes: a plurality of branches, each branch includes: - adder circuit 'is configured to add - feedback signal to - has The received input flash lock is configured to receive an output of the adder circuit in accordance with a clock signal; and a feedback circuit comprising: an evening device configured to receive an output of each branch as an input = the worker has a - clock select input, and is arranged to compose the output of each branch to form a full rate bit sequence; and an up-filter configured to be provided from each branch The 5H of the adder circuit has received input to eliminate inter-symbol interference (ISI). The DFE of claim 1 is wherein the filter comprises a continuous time infinite impulse response (IIR) filter having a frequency domain conversion function. The DFE of claim 1 further includes at least one additional latch coupled to the latch, each additional latch having a feedback loop for providing a feedback tap to the adder Circuitry to add this feedback tap to the received input. 4. ^Applicable to the DFE of the scope of the patent, wherein the latch comprises - a limiter of 0, such as the DFE of claim 4, wherein the limiter and the adder 201136248 are combined in a single stage Inside. 6. In the scope of claim 5, wherein each branch includes the limiter and the ageing circuit_single-stage, and the other includes the one-stage of the one-stage The flash locker keeps the data valid during the clock cycle. 7. The DFE of claim 6, wherein the flash lock comprises a regenerative latch. 8. The service of claim 1, wherein the multiplexer and the waver are combined in a single stage. 9. A method for decision feedback equalization, comprising: providing a 1/n rate decision feedback equalization circuit having a plurality of branches; using a adder circuit to pass a feedback signal from one or more branches to a Receiving the input sum; receiving a round of the adder circuit using a latch according to a clock signal; & feeding back an output of the latch to a multiplexer that receives the output of each branch input As a round-in, the multiplexer is arranged to combine the round-robin multiplex of each branch to a full-rate bit sequence; and use a continuous-time infinite impulse response (IIR) filter with a frequency domain conversion function. Inter-distance interference (ISI) from the received input is eliminated.丨0. The method of claim 9, further comprising providing a feedback tap to 25 201136248 the adder circuit ′ to add the feedback tap from the at least-extra flash lock to the received input. 11. The method of claim 9, wherein the locker and the adder circuit are combined in a single-language and the method further comprises using a dual-regeneration latch to regenerate an output of the single stage. a combined limiter and adder circuit comprising: a differential output line connected to a plurality of differential currents to be summed; and a resettable current comparison directly coupled to the differential output lines The load is configured to directly connect the summed differential current from the wire output line such that a sign is generated between the differential output lines based on the sign of the summed differential current Positive or negative differential voltage to lock a binary zero or _. 13. A limiter and adder circuit as claimed in claim 12, wherein the differential current comprises an input signal generated by a linear inductor, and at least one tap signal and a filter signal. One, which provides feedback as a decision feedback equalizer (DFE). 14. A limiter and adder circuit as claimed in claim 13 of the scope of the patent, further comprising a channel gate sample and hold circuit coupled to the linear inductance state for receiving a clock during an evaluation phase Switching to maintain the input signal of the k-number to the linear inductor constant. 15. A dual regenerative latch comprising two serially connected differential regenerative latch stages for improved speed and sensitivity 2011 26 201136248 degrees, the level comprising: a first stage having a a type of first input transistor, a cross-lighted load transistor, and a second type of reset transistor, and a second stage 'which has the second type of second input transistor and the first The type of intersection consumes the load transistor 'so that the first stage is in the non-permeabilized state, the reset transistor precharges the first-output to the power supply voltage, the second of the second stage The transistor is input to maintain the output at the level of the pre-discrimination storage bit. After the first stage is started, the first stage and the second stage are combined with the load transistor to start regeneration-input signal At the same time, the first-stage output microphone turns on the second-level human-electrode of the second-stage, and the second-stage includes the first-type cross-light load-carrying transistor, and the county-level The output is switched after reaching a critical signal level to provide additional regeneration . K is the dual regenerative locker of claim issuance, wherein the flash locker receives the output from the limiter, and the first limiter is still regenerated, so that the first stage and the first Limiting j 17. A dual regenerative flash locker according to claim 15 of the patent application, wherein the type comprises an NMOS and the second type comprises pM〇s. Class 18. The dual regenerative flash lock of item 15, wherein the type comprises a PMOS and the second type comprises NM〇s. The latch is used in a decision to apply for a dual-regeneration locker feedback equalizer (DFE). [S3 27 19. 201136248 20. The dual regenerative latch of claim 19, wherein the previously stored bit is a decision bit. 28