JP5502339B2 - 半導体装置及び半導体装置の製造方法 - Google Patents

半導体装置及び半導体装置の製造方法 Download PDF

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Publication number
JP5502339B2
JP5502339B2 JP2009034117A JP2009034117A JP5502339B2 JP 5502339 B2 JP5502339 B2 JP 5502339B2 JP 2009034117 A JP2009034117 A JP 2009034117A JP 2009034117 A JP2009034117 A JP 2009034117A JP 5502339 B2 JP5502339 B2 JP 5502339B2
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Japan
Prior art keywords
wiring
layer
semiconductor device
metal
resistance change
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Expired - Fee Related
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JP2009034117A
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English (en)
Japanese (ja)
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JP2010192605A (ja
JP2010192605A5 (enrdf_load_stackoverflow
Inventor
尚也 井上
喜宏 林
貴昭 金子
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Renesas Electronics Corp
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Renesas Electronics Corp
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Priority to JP2009034117A priority Critical patent/JP5502339B2/ja
Priority to US12/656,728 priority patent/US8390124B2/en
Publication of JP2010192605A publication Critical patent/JP2010192605A/ja
Publication of JP2010192605A5 publication Critical patent/JP2010192605A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/028—Formation of switching materials, e.g. deposition of layers by conversion of electrode material, e.g. oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2009034117A 2009-02-17 2009-02-17 半導体装置及び半導体装置の製造方法 Expired - Fee Related JP5502339B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009034117A JP5502339B2 (ja) 2009-02-17 2009-02-17 半導体装置及び半導体装置の製造方法
US12/656,728 US8390124B2 (en) 2009-02-17 2010-02-16 Semiconductor device and method of manufacturing semiconductor device including wiring via and switch via for connecting first and second wirings

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009034117A JP5502339B2 (ja) 2009-02-17 2009-02-17 半導体装置及び半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2010192605A JP2010192605A (ja) 2010-09-02
JP2010192605A5 JP2010192605A5 (enrdf_load_stackoverflow) 2012-03-15
JP5502339B2 true JP5502339B2 (ja) 2014-05-28

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JP2009034117A Expired - Fee Related JP5502339B2 (ja) 2009-02-17 2009-02-17 半導体装置及び半導体装置の製造方法

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Country Link
US (1) US8390124B2 (enrdf_load_stackoverflow)
JP (1) JP5502339B2 (enrdf_load_stackoverflow)

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JP5731904B2 (ja) * 2011-05-25 2015-06-10 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
US9343672B2 (en) * 2011-06-07 2016-05-17 Samsung Electronics Co., Ltd. Nonvolatile memory devices, nonvolatile memory cells and methods of manufacturing nonvolatile memory devices
US9577192B2 (en) * 2014-05-21 2017-02-21 Sony Semiconductor Solutions Corporation Method for forming a metal cap in a semiconductor memory device
WO2015182074A1 (ja) * 2014-05-29 2015-12-03 日本電気株式会社 半導体装置およびその製造方法
KR20160073796A (ko) * 2014-12-17 2016-06-27 에스케이하이닉스 주식회사 전자 장치 및 그 제조 방법
US10128438B2 (en) 2016-09-09 2018-11-13 Arm Limited CEM switching device
US10103327B2 (en) * 2016-09-14 2018-10-16 Arm Limited CEM switching device
US10121967B2 (en) 2016-11-29 2018-11-06 Arm Limited CEM switching device
CN108110022A (zh) * 2017-12-13 2018-06-01 德淮半导体有限公司 开关元件、及形成和使用开关元件的方法
US11636316B2 (en) 2018-01-31 2023-04-25 Cerfe Labs, Inc. Correlated electron switch elements for brain-based computing

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FR2771843B1 (fr) * 1997-11-28 2000-02-11 Sgs Thomson Microelectronics Transformateur en circuit integre
JP2001028397A (ja) 1999-05-10 2001-01-30 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP2004031439A (ja) * 2002-06-21 2004-01-29 Renesas Technology Corp 半導体集積回路装置およびその製造方法
JP4555540B2 (ja) * 2002-07-08 2010-10-06 ルネサスエレクトロニクス株式会社 半導体装置
US7115927B2 (en) * 2003-02-24 2006-10-03 Samsung Electronics Co., Ltd. Phase changeable memory devices
JP4634014B2 (ja) * 2003-05-22 2011-02-16 株式会社日立製作所 半導体記憶装置
CN100407400C (zh) * 2003-05-29 2008-07-30 日本电气株式会社 布线结构
JP3808866B2 (ja) * 2003-12-05 2006-08-16 株式会社東芝 半導体装置
US7052932B2 (en) * 2004-02-24 2006-05-30 Chartered Semiconductor Manufacturing Ltd. Oxygen doped SiC for Cu barrier and etch stop layer in dual damascene fabrication
JP2005252027A (ja) * 2004-03-04 2005-09-15 Nec Electronics Corp 多層配線構造の半導体装置
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US7351656B2 (en) * 2005-01-21 2008-04-01 Kabushiki Kaihsa Toshiba Semiconductor device having oxidized metal film and manufacture method of the same
JP2006319028A (ja) * 2005-05-11 2006-11-24 Nec Corp スイッチング素子、書き換え可能な論理集積回路、およびメモリ素子
JP2007042804A (ja) * 2005-08-02 2007-02-15 Renesas Technology Corp 半導体装置およびその製造方法
JP5263856B2 (ja) 2006-07-26 2013-08-14 独立行政法人産業技術総合研究所 スイッチング素子及びその製造方法
US7586175B2 (en) * 2006-10-23 2009-09-08 Samsung Electronics Co., Ltd. Semiconductor wafer having embedded electroplating current paths to provide uniform plating over wafer surface
DE102007050610A1 (de) * 2006-10-24 2008-05-08 Denso Corp., Kariya Halbleitervorrichtung, Verdrahtung einer Halbleitervorrichtung und Verfahren zum Bilden einer Verdrahtung
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WO2008126197A1 (ja) * 2007-03-20 2008-10-23 Fujitsu Microelectronics Limited 半導体装置の製造方法
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JP5424551B2 (ja) * 2007-11-07 2014-02-26 ローム株式会社 半導体装置
EP2219221A4 (en) * 2007-11-29 2013-03-13 Panasonic Corp NON-VOLATILE MEMORY ARRANGEMENT AND METHOD FOR THE PRODUCTION THEREOF
EP2234160B1 (en) * 2007-12-26 2014-02-26 Panasonic Corporation Nonvolatile semiconductor storage device and method for manufacturing the same
DE102008016431B4 (de) * 2008-03-31 2010-06-02 Advanced Micro Devices, Inc., Sunnyvale Metalldeckschicht mit erhöhtem Elektrodenpotential für kupferbasierte Metallgebiete in Halbleiterbauelementen sowie Verfahren zu ihrer Herstellung

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Publication number Publication date
JP2010192605A (ja) 2010-09-02
US20100207093A1 (en) 2010-08-19
US8390124B2 (en) 2013-03-05

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