WO2008126197A1 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
WO2008126197A1
WO2008126197A1 PCT/JP2007/055662 JP2007055662W WO2008126197A1 WO 2008126197 A1 WO2008126197 A1 WO 2008126197A1 JP 2007055662 W JP2007055662 W JP 2007055662W WO 2008126197 A1 WO2008126197 A1 WO 2008126197A1
Authority
WO
WIPO (PCT)
Prior art keywords
oxide film
aluminum oxide
semiconductor device
films
resist pattern
Prior art date
Application number
PCT/JP2007/055662
Other languages
English (en)
French (fr)
Inventor
Kouichi Nagai
Original Assignee
Fujitsu Microelectronics Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Microelectronics Limited filed Critical Fujitsu Microelectronics Limited
Priority to PCT/JP2007/055662 priority Critical patent/WO2008126197A1/ja
Priority to KR1020097017672A priority patent/KR101046268B1/ko
Priority to JP2009508748A priority patent/JP5035336B2/ja
Publication of WO2008126197A1 publication Critical patent/WO2008126197A1/ja
Priority to US12/539,200 priority patent/US8658493B2/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/40—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the peripheral circuit region
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Formation Of Insulating Films (AREA)
  • Non-Volatile Memory (AREA)

Abstract

　強誘電体キャパシタを覆うアルミニウム酸化膜を形成する。次に、アルミニウム酸化膜に、上部電極の一部を露出する開口部（５１ｔ）及び下部電極の一部を露出する開口部（５１ｂ）を形成する。その後、膜（２３～２６）を形成し、レジストパターン（９２）を形成する。そして、レジストパターン（９２）をマスクとして膜（２３～２６）のエッチングを行うことにより、コンタクトホール（２７ｔ）及び（２７ｂ）を形成する。この時、アルミニウム酸化膜に開口部（５１ｔ）及び（５１ｂ）が形成されているため、アルミニウム酸化膜を加工する必要がない。従って、容易にコンタクトホール（２７ｔ）及び（２７ｂ）を形成することができる。
PCT/JP2007/055662 2007-03-20 2007-03-20 半導体装置の製造方法 WO2008126197A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/JP2007/055662 WO2008126197A1 (ja) 2007-03-20 2007-03-20 半導体装置の製造方法
KR1020097017672A KR101046268B1 (ko) 2007-03-20 2007-03-20 반도체장치의 제조방법
JP2009508748A JP5035336B2 (ja) 2007-03-20 2007-03-20 半導体装置の製造方法
US12/539,200 US8658493B2 (en) 2007-03-20 2009-08-11 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/055662 WO2008126197A1 (ja) 2007-03-20 2007-03-20 半導体装置の製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/539,200 Continuation US8658493B2 (en) 2007-03-20 2009-08-11 Manufacturing method of semiconductor device

Publications (1)

Publication Number Publication Date
WO2008126197A1 true WO2008126197A1 (ja) 2008-10-23

Family

ID=39863381

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/055662 WO2008126197A1 (ja) 2007-03-20 2007-03-20 半導体装置の製造方法

Country Status (4)

Country Link
US (1) US8658493B2 (ja)
JP (1) JP5035336B2 (ja)
KR (1) KR101046268B1 (ja)
WO (1) WO2008126197A1 (ja)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009231445A (ja) * 2008-03-21 2009-10-08 Toshiba Corp 半導体記憶装置
JP5502339B2 (ja) * 2009-02-17 2014-05-28 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
KR102546639B1 (ko) 2017-11-21 2023-06-23 삼성전자주식회사 반도체 장치
JP7027916B2 (ja) 2018-01-31 2022-03-02 富士通セミコンダクターメモリソリューション株式会社 半導体装置及びその製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006049795A (ja) * 2004-06-28 2006-02-16 Fujitsu Ltd 半導体装置及びその製造方法
JP2006202988A (ja) * 2005-01-20 2006-08-03 Fujitsu Ltd 半導体装置及びその製造方法
JP2007067241A (ja) * 2005-08-31 2007-03-15 Fujitsu Ltd 半導体装置の製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3165093B2 (ja) * 1997-11-13 2001-05-14 松下電子工業株式会社 半導体装置およびその製造方法
JP3144405B2 (ja) 1998-11-25 2001-03-12 日本電気株式会社 半導体記憶装置の製造方法
JP3907921B2 (ja) * 2000-06-19 2007-04-18 富士通株式会社 半導体装置の製造方法
JP2003100994A (ja) 2001-09-27 2003-04-04 Oki Electric Ind Co Ltd 強誘電体メモリおよびその製造方法
JP2003152165A (ja) * 2001-11-15 2003-05-23 Fujitsu Ltd 半導体装置およびその製造方法
JP4756915B2 (ja) * 2005-05-31 2011-08-24 Ｏｋｉセミコンダクタ株式会社 強誘電体メモリ装置及びその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006049795A (ja) * 2004-06-28 2006-02-16 Fujitsu Ltd 半導体装置及びその製造方法
JP2006202988A (ja) * 2005-01-20 2006-08-03 Fujitsu Ltd 半導体装置及びその製造方法
JP2007067241A (ja) * 2005-08-31 2007-03-15 Fujitsu Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
JPWO2008126197A1 (ja) 2010-07-22
JP5035336B2 (ja) 2012-09-26
KR20100004981A (ko) 2010-01-13
US20090298203A1 (en) 2009-12-03
US8658493B2 (en) 2014-02-25
KR101046268B1 (ko) 2011-07-05

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