JP2007067241A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP2007067241A JP2007067241A JP2005252724A JP2005252724A JP2007067241A JP 2007067241 A JP2007067241 A JP 2007067241A JP 2005252724 A JP2005252724 A JP 2005252724A JP 2005252724 A JP2005252724 A JP 2005252724A JP 2007067241 A JP2007067241 A JP 2007067241A
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- Prior art keywords
- insulating film
- film
- capacitor
- forming
- semiconductor device
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
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- H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
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- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
【解決手段】 シリコン基板1上に第1絶縁膜11を形成する工程と、第1絶縁膜11上に、下部電極15a、強誘電体材料で構成されるキャパシタ誘電体膜16a、及び上部電極17aを順に積層してなるキャパシタQを形成する工程と、キャパシタQと第1絶縁膜11とを覆う第1キャパシタ保護絶縁膜19として、触媒CVD法により窒化シリコン膜を形成する工程と、第1キャパシタ保護絶縁膜19の上に第2絶縁膜20を形成する工程と、を有する半導体装置の製造方法による。
【選択図】 図12
Description
本実施形態の説明に先立ち、本発明の予備的事項について説明する。
図6〜図12は、本実施形態に係る半導体装置の製造途中の断面図である。なお、これらの図において、図1〜図5で説明した要素にはこれらの図におけるのと同じ符号を付し、以下ではその説明を省略する。
前記第1絶縁膜上に、下部電極、強誘電体材料で構成されるキャパシタ誘電体膜、及び上部電極を順に積層してなるキャパシタを形成する工程と、
前記キャパシタと前記第1絶縁膜とを覆う第1キャパシタ保護絶縁膜として、触媒CVD法により窒化シリコン膜を形成する工程と、
前記第1キャパシタ保護絶縁膜の上に第2絶縁膜を形成する工程と、
を有することを特徴とする半導体装置の製造方法。
前記第1絶縁膜上に、第1導電膜、強誘電体膜、及び第2導電膜を順に形成する工程と、
前記第2導電膜をパターニングして前記上部電極にする工程と、
前記強誘電体膜をパターニングして前記キャパシタ誘電体膜にする工程と、
前記上部電極、前記キャパシタ誘電体膜、及び前記第1導電膜を覆う第2キャパシタ保護絶縁膜として金属酸化膜を形成する工程と、
前記第2キャパシタ保護絶縁膜と前記第1導電膜とをパターニングすることにより、前記第1導電膜を前記下部電極にすると共に、該下部電極、前記キャパシタ誘電体膜、及び前記上部電極の上にのみ前記第2キャパシタ保護絶縁膜を残す工程とを有することを特徴とする付記1に記載の半導体装置の製造方法。
前記不純物拡散領域の上の前記第1絶縁膜、前記第1キャパシタ保護絶縁膜、及び前記第2絶縁膜にホールを形成する工程と、
前記ホール内に、前記不純物拡散領域と電気的に接続されたコンタクトプラグを形成する工程とを有することを特徴とする付記1に記載の半導体装置の製造方法。
前記金属配線上に層間絶縁膜を形成する工程とを有し、
前記金属配線と前記層間絶縁膜との間、又は該層間絶縁膜の上面に、第3キャパシタ保護絶縁膜として触媒CVD法により窒化シリコン膜を形成することを特徴とする付記1に記載の半導体装置の製造方法。
前記層間絶縁膜を形成する工程において、プラズマCVD法により該層間絶縁膜を形成することを特徴とする付記10に記載の半導体装置の製造方法。
前記第1絶縁膜上に、下部電極、強誘電体材料で構成されるキャパシタ誘電体膜、及び上部電極を順に積層してなるキャパシタを形成する工程と、
前記キャパシタを覆う第2絶縁膜を形成する工程と、
前記第2絶縁膜上に金属配線を形成する工程と、
前記金属配線上に、第1キャパシタ保護絶縁膜として触媒CVD法により窒化シリコン膜を形成する工程と、
前記第1キャパシタ保護絶縁膜上に層間絶縁膜を形成する工程と、
を有することを特徴とする半導体装置の製造方法。
前記層間絶縁膜を形成する工程において、プラズマCVD法により該層間絶縁膜を形成することを特徴とする付記13に記載の半導体装置の製造方法。
前記ホール内に、前記金属配線と電気的に接続されたコンタクトプラグを形成する工程とを有することを特徴とする付記13に記載の半導体装置の製造方法。
Claims (10)
- 半導体基板上に第1絶縁膜を形成する工程と、
前記第1絶縁膜上に、下部電極、強誘電体材料で構成されるキャパシタ誘電体膜、及び上部電極を順に積層してなるキャパシタを形成する工程と、
前記キャパシタと前記第1絶縁膜とを覆う第1キャパシタ保護絶縁膜として、触媒CVD法により窒化シリコン膜を形成する工程と、
前記第1キャパシタ保護絶縁膜の上に第2絶縁膜を形成する工程と、
を有することを特徴とする半導体装置の製造方法。 - 前記第1キャパシタ保護絶縁膜を形成する工程において、基板温度を200℃以下にすることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記キャパシタを形成する工程は、
前記第1絶縁膜上に、第1導電膜、強誘電体膜、及び第2導電膜を順に形成する工程と、
前記第2導電膜をパターニングして前記上部電極にする工程と、
前記強誘電体膜をパターニングして前記キャパシタ誘電体膜にする工程と、
前記上部電極、前記キャパシタ誘電体膜、及び前記第1導電膜を覆う第2キャパシタ保護絶縁膜として金属酸化膜を形成する工程と、
前記第2キャパシタ保護絶縁膜と前記第1導電膜とをパターニングすることにより、前記第1導電膜を前記下部電極にすると共に、該下部電極、前記キャパシタ誘電体膜、及び前記上部電極の上にのみ前記第2キャパシタ保護絶縁膜を残す工程とを有することを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記第2キャパシタ保護絶縁膜を形成する工程の後であって、前記第1キャパシタ保護絶縁膜を形成する工程の前に、酸素含有雰囲気中で前記キャパシタ誘電体膜をアニールする工程を有することを特徴とする請求項4に記載の半導体装置の製造方法。
- 前記半導体基板に不純物拡散領域を形成する工程と、
前記不純物拡散領域の上の前記第1絶縁膜、前記第1キャパシタ保護絶縁膜、及び前記第2絶縁膜にホールを形成する工程と、
前記ホール内に、前記不純物拡散領域と電気的に接続されたコンタクトプラグを形成する工程とを有することを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記第2絶縁膜上に金属配線を形成する工程と、
前記金属配線上に層間絶縁膜を形成する工程とを有し、
前記金属配線と前記層間絶縁膜との間、又は該層間絶縁膜の上面に、第3キャパシタ保護絶縁膜として触媒CVD法により窒化シリコン膜を形成することを特徴とする請求項1に記載の半導体装置の製造方法。 - 半導体基板上に第1絶縁膜を形成する工程と、
前記第1絶縁膜上に、下部電極、強誘電体材料で構成されるキャパシタ誘電体膜、及び上部電極を順に積層してなるキャパシタを形成する工程と、
前記キャパシタを覆う第2絶縁膜を形成する工程と、
前記第2絶縁膜上に金属配線を形成する工程と、
前記金属配線上に、第1キャパシタ保護絶縁膜として触媒CVD法により窒化シリコン膜を形成する工程と、
前記第1キャパシタ保護絶縁膜上に層間絶縁膜を形成する工程と、
を有することを特徴とする半導体装置の製造方法。 - 前記金属配線を形成する工程において、該金属配線の構成材料としてアルミニウムを採用し、
前記層間絶縁膜を形成する工程において、プラズマCVD法により該層間絶縁膜を形成することを特徴とする請求項7に記載の半導体装置の製造方法。 - 前記金属配線の上の前記第1キャパシタ保護絶縁膜と前記層間絶縁膜とにホールを形成する工程と、
前記ホール内に、前記金属配線と電気的に接続されたコンタクトプラグを形成する工程とを有することを特徴とする請求項7に記載の半導体装置の製造方法。 - 前記層間絶縁膜上に、第2キャパシタ保護絶縁膜として触媒CVD法により窒化シリコン膜を形成する工程を有することを特徴とする請求項7に記載の半導体装置の製造方法。
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WO2008126197A1 (ja) * | 2007-03-20 | 2008-10-23 | Fujitsu Microelectronics Limited | 半導体装置の製造方法 |
JP2013211578A (ja) * | 2013-05-20 | 2013-10-10 | Fujitsu Semiconductor Ltd | 半導体装置の製造方法 |
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WO2008102438A1 (ja) * | 2007-02-21 | 2008-08-28 | Fujitsu Microelectronics Limited | 半導体装置及びその製造方法 |
JP2008300557A (ja) * | 2007-05-30 | 2008-12-11 | Mitsubishi Electric Corp | 半導体装置 |
US9299956B2 (en) * | 2012-06-13 | 2016-03-29 | Aixtron, Inc. | Method for deposition of high-performance coatings and encapsulated electronic devices |
KR102546639B1 (ko) | 2017-11-21 | 2023-06-23 | 삼성전자주식회사 | 반도체 장치 |
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