JP5496184B2 - キャパシタレスメモリ素子 - Google Patents

キャパシタレスメモリ素子 Download PDF

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Publication number
JP5496184B2
JP5496184B2 JP2011507351A JP2011507351A JP5496184B2 JP 5496184 B2 JP5496184 B2 JP 5496184B2 JP 2011507351 A JP2011507351 A JP 2011507351A JP 2011507351 A JP2011507351 A JP 2011507351A JP 5496184 B2 JP5496184 B2 JP 5496184B2
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Japan
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layer
memory device
gate electrode
region
voltage
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JP2011507351A
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English (en)
Japanese (ja)
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JP2011519483A5 (enExample
JP2011519483A (ja
Inventor
ジェ−グン パク
テ−フン シム
ゴン−スプ イ
ソン−ジェ キム
テ−ヒュン キム
Original Assignee
インダストリー−ユニバーシティー コオペレーション ファウンデーション ハンヤン ユニバーシティー
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/694—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/711—Insulated-gate field-effect transistors [IGFET] having floating bodies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/4016—Memory devices with silicon-on-insulator cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6748—Group IV materials, e.g. germanium or silicon carbide having a multilayer structure or superlattice structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
JP2011507351A 2008-04-30 2009-04-30 キャパシタレスメモリ素子 Active JP5496184B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR10-2008-0040888 2008-04-30
KR1020080040888A KR101505494B1 (ko) 2008-04-30 2008-04-30 무 커패시터 메모리 소자
PCT/KR2009/002284 WO2009134089A2 (ko) 2008-04-30 2009-04-30 무 커패시터 메모리 소자

Publications (3)

Publication Number Publication Date
JP2011519483A JP2011519483A (ja) 2011-07-07
JP2011519483A5 JP2011519483A5 (enExample) 2011-11-04
JP5496184B2 true JP5496184B2 (ja) 2014-05-21

Family

ID=41255563

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011507351A Active JP5496184B2 (ja) 2008-04-30 2009-04-30 キャパシタレスメモリ素子

Country Status (6)

Country Link
US (1) US8860109B2 (enExample)
EP (1) EP2284879B1 (enExample)
JP (1) JP5496184B2 (enExample)
KR (1) KR101505494B1 (enExample)
TW (1) TWI419327B (enExample)
WO (1) WO2009134089A2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9660024B2 (en) 2014-12-18 2017-05-23 Samsung Electronics Co., Ltd. Semiconductor device with two transistors and a capacitor

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* Cited by examiner, † Cited by third party
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US8330170B2 (en) 2008-12-05 2012-12-11 Micron Technology, Inc. Semiconductor device structures including transistors with energy barriers adjacent to transistor channels and associated methods
US9105707B2 (en) 2013-07-24 2015-08-11 International Business Machines Corporation ZRAM heterochannel memory
US10403628B2 (en) 2014-12-23 2019-09-03 International Business Machines Corporation Finfet based ZRAM with convex channel region
US9978772B1 (en) 2017-03-14 2018-05-22 Micron Technology, Inc. Memory cells and integrated structures
US11056571B2 (en) * 2019-06-18 2021-07-06 Micron Technology, Inc. Memory cells and integrated structures

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JPS5840855A (ja) * 1981-09-04 1983-03-09 Hitachi Ltd 半導体記憶素子
JPH06177375A (ja) * 1992-12-10 1994-06-24 Hitachi Ltd 半導体装置及びその製造方法
JP3361922B2 (ja) * 1994-09-13 2003-01-07 株式会社東芝 半導体装置
JP3407232B2 (ja) * 1995-02-08 2003-05-19 富士通株式会社 半導体記憶装置及びその動作方法
JPH1092952A (ja) * 1996-09-18 1998-04-10 Toshiba Corp 半導体記憶装置
US5963817A (en) * 1997-10-16 1999-10-05 International Business Machines Corporation Bulk and strained silicon on insulator using local selective oxidation
KR100257765B1 (ko) * 1997-12-30 2000-06-01 김영환 기억소자 및 그 제조 방법
JP4713783B2 (ja) * 2000-08-17 2011-06-29 株式会社東芝 半導体メモリ装置
JP3884266B2 (ja) * 2001-02-19 2007-02-21 株式会社東芝 半導体メモリ装置及びその製造方法
JP2003031693A (ja) * 2001-07-19 2003-01-31 Toshiba Corp 半導体メモリ装置
KR20030034470A (ko) * 2001-10-23 2003-05-09 주식회사 하이닉스반도체 실리콘-게르마늄 채널을 포함하는 트랜지스터의 제조방법
JP3782021B2 (ja) * 2002-02-22 2006-06-07 株式会社東芝 半導体装置、半導体装置の製造方法、半導体基板の製造方法
JP4880867B2 (ja) * 2002-04-10 2012-02-22 セイコーインスツル株式会社 薄膜メモリ、アレイとその動作方法および製造方法
US7042052B2 (en) * 2003-02-10 2006-05-09 Micron Technology, Inc. Transistor constructions and electronic devices
US7045401B2 (en) * 2003-06-23 2006-05-16 Sharp Laboratories Of America, Inc. Strained silicon finFET device
US6921982B2 (en) * 2003-07-21 2005-07-26 International Business Machines Corporation FET channel having a strained lattice structure along multiple surfaces
US20050062088A1 (en) * 2003-09-22 2005-03-24 Texas Instruments Incorporated Multi-gate one-transistor dynamic random access memory
US7057216B2 (en) 2003-10-31 2006-06-06 International Business Machines Corporation High mobility heterojunction complementary field effect transistors and methods thereof
US7244958B2 (en) 2004-06-24 2007-07-17 International Business Machines Corporation Integration of strained Ge into advanced CMOS technology
US7193279B2 (en) * 2005-01-18 2007-03-20 Intel Corporation Non-planar MOS structure with a strained channel region
JP4239203B2 (ja) * 2005-05-31 2009-03-18 株式会社東芝 半導体装置とその製造方法
US7517741B2 (en) * 2005-06-30 2009-04-14 Freescale Semiconductor, Inc. Single transistor memory cell with reduced recombination rates
US8410539B2 (en) 2006-02-14 2013-04-02 Stmicroelectronics (Crolles 2) Sas MOS transistor with a settable threshold
JP2008213624A (ja) 2007-03-02 2008-09-18 Toyota Motor Corp 操作機構および操作機構を備えた車両
US7928426B2 (en) * 2007-03-27 2011-04-19 Intel Corporation Forming a non-planar transistor having a quantum well channel
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9660024B2 (en) 2014-12-18 2017-05-23 Samsung Electronics Co., Ltd. Semiconductor device with two transistors and a capacitor

Also Published As

Publication number Publication date
KR101505494B1 (ko) 2015-03-24
EP2284879A4 (en) 2012-05-23
EP2284879A2 (en) 2011-02-16
EP2284879B1 (en) 2020-05-06
KR20090114981A (ko) 2009-11-04
WO2009134089A3 (ko) 2010-02-11
TWI419327B (zh) 2013-12-11
WO2009134089A2 (ko) 2009-11-05
US20110127580A1 (en) 2011-06-02
JP2011519483A (ja) 2011-07-07
TW200950088A (en) 2009-12-01
US8860109B2 (en) 2014-10-14

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