JP5965386B2 - トランジスタを備えるramメモリセル - Google Patents
トランジスタを備えるramメモリセル Download PDFInfo
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- JP5965386B2 JP5965386B2 JP2013503163A JP2013503163A JP5965386B2 JP 5965386 B2 JP5965386 B2 JP 5965386B2 JP 2013503163 A JP2013503163 A JP 2013503163A JP 2013503163 A JP2013503163 A JP 2013503163A JP 5965386 B2 JP5965386 B2 JP 5965386B2
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- 239000000758 substrate Substances 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 230000014759 maintenance of location Effects 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
- H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/36—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being a FinFET
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/4016—Memory devices with silicon-on-insulator cells
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
- Thin Film Transistor (AREA)
- Dram (AREA)
Description
前記ドレインに正電圧を印加し、該正電圧を印加する間前記ゲートに短い正電圧を印加する「1」を書き込む工程、
前記ドレインに極めて微小な正電圧、ゼロ電圧又は負電圧を印加し、前記ゲートに正電圧を印加する「0」を書き込む工程、
前記ゲートに負電圧を印加して前記ドレインに微小の正電圧を印加して読み出す工程、及び
前記ゲートに負電圧を印加して前記ドレインに微小な正電圧又はゼロ電圧を印加して維持する工程
を任意の順序で有することを特徴とする方法を提供する。
Claims (8)
- ドレイン、ソース、及び、絶縁ゲートで覆われた中央領域を含み、絶縁層上に広がっている半導体層中に形成されたMOSトランジスタで構成されたメモリセルであって、
前記中央領域は、ゲート面に平行に延在する互いに逆の導電型を有する第1及び第2の領域に前記中央領域の厚さ方向で分けられ、
前記第1及び第2の領域のうちの前記ゲートに近い一方の領域は、前記ドレイン及びソースの導電型と逆の導電型を有しており、
前記第1及び第2の領域のうちの他方の領域は、前記絶縁層上に広がって、前記ドレイン及びソースの導電型と同じ導電型を有しており、
前記第1及び第2の領域のうちの前記一方の領域は、5から50nmの範囲の厚さを有し、ドーピングレベルは10 16 atoms/cm 3 より小さい
ことを特徴とするメモリセル。 - SOI構造から構成されることを特徴とする請求項1に記載のメモリセル。
- 前記絶縁層は、前記ドレイン及びソースの導電型と逆の導電型を有する半導体基板によって支持されていることを特徴とする請求項1に記載のメモリセル。
- FINFET構造から構成されることを特徴とする請求項1に記載のメモリセル。
- 前記第1及び第2の領域のうちの前記ゲートに遠い前記他方の領域は、5から50nmの範囲の厚さを有し、ドーピングレベルは1016atoms/cm3 と1018atoms/cm3 との間の範囲であることを特徴とする請求項1乃至3のいずれか1項に記載のメモリセル。
- 前記第1及び第2の領域のうちの前記一方の領域は、10から20nmの厚さを有することを特徴とする請求項1乃至3及び5のいずれか1項に記載のメモリセル。
- 前記第1及び第2の領域のうちの前記ゲートに遠い前記他方の領域は、10から40nmの範囲の厚さを有し、ドーピングレベルは1016atoms/cm3 と1018atoms/cm3 との間の範囲であることを特徴とする請求項1乃至3、5及び6のいずれか1項に記載のメモリセル。
- ドレイン、ソース、及び、絶縁ゲートで覆われた中央領域を含み、絶縁層上に広がっている半導体層中に形成されたMOSトランジスタで構成されたメモリセルであって、前記中央領域は、ゲート面に平行に延在する互いに逆の導電型を有する第1及び第2の領域に前記中央領域の厚さ方向で分けられ、前記第1及び第2の領域のうちの前記ゲートに近い一方の領域は、前記ドレイン及びソースの導電型と逆の導電型を有しており、前記第1及び第2の領域のうちの他方の領域は、前記絶縁層上に広がって、前記ドレイン及びソースの導電型と同じ導電型を有しているメモリセルを使用する方法であって、
前記ソースの電圧は参照電圧として見なされ、前記ソース及びドレイン領域はN型である場合に、
前記ドレインに正電圧を印加し、該正電圧を印加する間前記ゲートに短い正電圧を印加する「1」を書き込む工程、
前記ドレインに極めて微小な正電圧、ゼロ電圧又は負電圧を印加し、前記ゲートに正電圧を印加する「0」を書き込む工程、
前記ゲートに負電圧を印加して前記ドレインに微小の正電圧を印加して読み出す工程、及び
前記ゲートに負電圧を印加して前記ドレインに微小な正電圧又はゼロ電圧を印加して維持する工程
を任意の順序で有することを特徴とする方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1052612A FR2958779B1 (fr) | 2010-04-07 | 2010-04-07 | Point memoire ram a un transistor |
FR1052612 | 2010-04-07 | ||
PCT/FR2011/050788 WO2011124855A1 (fr) | 2010-04-07 | 2011-04-07 | Point memoire ram a un transistor |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013527977A JP2013527977A (ja) | 2013-07-04 |
JP5965386B2 true JP5965386B2 (ja) | 2016-08-03 |
Family
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Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013503163A Active JP5965386B2 (ja) | 2010-04-07 | 2011-04-07 | トランジスタを備えるramメモリセル |
Country Status (6)
Country | Link |
---|---|
US (1) | US9166051B2 (ja) |
EP (1) | EP2556533B1 (ja) |
JP (1) | JP5965386B2 (ja) |
KR (1) | KR101804197B1 (ja) |
FR (1) | FR2958779B1 (ja) |
WO (1) | WO2011124855A1 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2980918B1 (fr) * | 2011-10-04 | 2014-03-07 | Univ Granada | Point memoire ram a un transistor |
FR3070788B1 (fr) | 2017-09-04 | 2021-07-30 | Commissariat Energie Atomique | Procede de programmation d’une cellule memoire dram a un transistor et dispositif memoire |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4021835A (en) * | 1974-01-25 | 1977-05-03 | Hitachi, Ltd. | Semiconductor device and a method for fabricating the same |
US4276095A (en) * | 1977-08-31 | 1981-06-30 | International Business Machines Corporation | Method of making a MOSFET device with reduced sensitivity of threshold voltage to source to substrate voltage variations |
US4596068A (en) * | 1983-12-28 | 1986-06-24 | Harris Corporation | Process for minimizing boron depletion in N-channel FET at the silicon-silicon oxide interface |
JPS62128175A (ja) * | 1985-11-29 | 1987-06-10 | Hitachi Ltd | 半導体装置 |
WO1988008617A1 (en) * | 1987-04-20 | 1988-11-03 | Research Corporation Technologies, Inc. | Buried well dram |
US5118632A (en) * | 1989-10-20 | 1992-06-02 | Harris Corporation | Dual layer surface gate JFET having enhanced gate-channel breakdown voltage |
JP2899122B2 (ja) * | 1991-03-18 | 1999-06-02 | キヤノン株式会社 | 絶縁ゲートトランジスタ及び半導体集積回路 |
US5463237A (en) * | 1993-11-04 | 1995-10-31 | Victor Company Of Japan, Ltd. | MOSFET device having depletion layer |
US5698884A (en) * | 1996-02-07 | 1997-12-16 | Thunderbird Technologies, Inc. | Short channel fermi-threshold field effect transistors including drain field termination region and methods of fabricating same |
US6245607B1 (en) * | 1998-12-28 | 2001-06-12 | Industrial Technology Research Institute | Buried channel quasi-unipolar transistor |
JP4713783B2 (ja) | 2000-08-17 | 2011-06-29 | 株式会社東芝 | 半導体メモリ装置 |
US6555872B1 (en) * | 2000-11-22 | 2003-04-29 | Thunderbird Technologies, Inc. | Trench gate fermi-threshold field effect transistors |
GB2431774B (en) * | 2004-07-30 | 2009-04-01 | Advanced Micro Devices Inc | Self-biasing transistor structure and SRAM cell |
DE102004037087A1 (de) * | 2004-07-30 | 2006-03-23 | Advanced Micro Devices, Inc., Sunnyvale | Selbstvorspannende Transistorstruktur und SRAM-Zellen mit weniger als sechs Transistoren |
JP4660324B2 (ja) | 2005-09-06 | 2011-03-30 | 株式会社東芝 | Fbcメモリ装置 |
DE102006004409A1 (de) * | 2006-01-31 | 2007-08-09 | Advanced Micro Devices, Inc., Sunnyvale | SRAM-Zelle mit selbststabilisierenden Transistorstrukturen |
KR101324196B1 (ko) * | 2007-06-05 | 2013-11-06 | 삼성전자주식회사 | 커패시터리스 디램 및 그의 제조방법 |
KR20090011886A (ko) | 2007-07-27 | 2009-02-02 | 삼성전자주식회사 | 커패시터리스 디램 및 그의 제조 및 동작방법 |
DE102008007029B4 (de) * | 2008-01-31 | 2014-07-03 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Betrieb einer elektronischen Schaltung mit körpergesteuertem Doppelkanaltransistor und SRAM-Zelle mit körpergesteuertem Doppelkanaltransistor |
US8014200B2 (en) * | 2008-04-08 | 2011-09-06 | Zeno Semiconductor, Inc. | Semiconductor memory having volatile and multi-bit, non-volatile functionality and methods of operating |
FR2944641B1 (fr) * | 2009-04-15 | 2011-04-29 | Centre Nat Rech Scient | Point memoire ram a un transistor. |
-
2010
- 2010-04-07 FR FR1052612A patent/FR2958779B1/fr active Active
-
2011
- 2011-04-07 WO PCT/FR2011/050788 patent/WO2011124855A1/fr active Application Filing
- 2011-04-07 JP JP2013503163A patent/JP5965386B2/ja active Active
- 2011-04-07 EP EP11718462.2A patent/EP2556533B1/fr active Active
- 2011-04-07 KR KR1020127028931A patent/KR101804197B1/ko active IP Right Grant
- 2011-04-07 US US13/639,672 patent/US9166051B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
FR2958779A1 (fr) | 2011-10-14 |
EP2556533A1 (fr) | 2013-02-13 |
WO2011124855A1 (fr) | 2011-10-13 |
US9166051B2 (en) | 2015-10-20 |
EP2556533B1 (fr) | 2020-10-07 |
US20130148441A1 (en) | 2013-06-13 |
JP2013527977A (ja) | 2013-07-04 |
FR2958779B1 (fr) | 2015-07-17 |
KR101804197B1 (ko) | 2017-12-04 |
KR20130098145A (ko) | 2013-09-04 |
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