KR101505494B1 - 무 커패시터 메모리 소자 - Google Patents

무 커패시터 메모리 소자 Download PDF

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KR101505494B1
KR101505494B1 KR1020080040888A KR20080040888A KR101505494B1 KR 101505494 B1 KR101505494 B1 KR 101505494B1 KR 1020080040888 A KR1020080040888 A KR 1020080040888A KR 20080040888 A KR20080040888 A KR 20080040888A KR 101505494 B1 KR101505494 B1 KR 101505494B1
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South Korea
Prior art keywords
layer
gate electrode
region
channel region
voltage
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KR1020080040888A
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English (en)
Korean (ko)
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KR20090114981A (ko
Inventor
박재근
심태헌
이곤섭
김성제
김태현
Original Assignee
한양대학교 산학협력단
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Priority to KR1020080040888A priority Critical patent/KR101505494B1/ko
Priority to PCT/KR2009/002284 priority patent/WO2009134089A2/ko
Priority to JP2011507351A priority patent/JP5496184B2/ja
Priority to EP09738995.1A priority patent/EP2284879B1/en
Priority to US12/990,353 priority patent/US8860109B2/en
Priority to TW098114394A priority patent/TWI419327B/zh
Publication of KR20090114981A publication Critical patent/KR20090114981A/ko
Application granted granted Critical
Publication of KR101505494B1 publication Critical patent/KR101505494B1/ko
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/694—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/711—Insulated-gate field-effect transistors [IGFET] having floating bodies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/4016—Memory devices with silicon-on-insulator cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6748—Group IV materials, e.g. germanium or silicon carbide having a multilayer structure or superlattice structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
KR1020080040888A 2008-04-30 2008-04-30 무 커패시터 메모리 소자 Active KR101505494B1 (ko)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1020080040888A KR101505494B1 (ko) 2008-04-30 2008-04-30 무 커패시터 메모리 소자
PCT/KR2009/002284 WO2009134089A2 (ko) 2008-04-30 2009-04-30 무 커패시터 메모리 소자
JP2011507351A JP5496184B2 (ja) 2008-04-30 2009-04-30 キャパシタレスメモリ素子
EP09738995.1A EP2284879B1 (en) 2008-04-30 2009-04-30 Capacitor-less memory device
US12/990,353 US8860109B2 (en) 2008-04-30 2009-04-30 Capacitor-less memory device
TW098114394A TWI419327B (zh) 2008-04-30 2009-04-30 無電容記憶體元件

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080040888A KR101505494B1 (ko) 2008-04-30 2008-04-30 무 커패시터 메모리 소자

Publications (2)

Publication Number Publication Date
KR20090114981A KR20090114981A (ko) 2009-11-04
KR101505494B1 true KR101505494B1 (ko) 2015-03-24

Family

ID=41255563

Family Applications (1)

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KR1020080040888A Active KR101505494B1 (ko) 2008-04-30 2008-04-30 무 커패시터 메모리 소자

Country Status (6)

Country Link
US (1) US8860109B2 (enExample)
EP (1) EP2284879B1 (enExample)
JP (1) JP5496184B2 (enExample)
KR (1) KR101505494B1 (enExample)
TW (1) TWI419327B (enExample)
WO (1) WO2009134089A2 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8330170B2 (en) 2008-12-05 2012-12-11 Micron Technology, Inc. Semiconductor device structures including transistors with energy barriers adjacent to transistor channels and associated methods
US9105707B2 (en) 2013-07-24 2015-08-11 International Business Machines Corporation ZRAM heterochannel memory
KR20160074826A (ko) 2014-12-18 2016-06-29 삼성전자주식회사 반도체 장치
US10403628B2 (en) 2014-12-23 2019-09-03 International Business Machines Corporation Finfet based ZRAM with convex channel region
US9978772B1 (en) 2017-03-14 2018-05-22 Micron Technology, Inc. Memory cells and integrated structures
US11056571B2 (en) * 2019-06-18 2021-07-06 Micron Technology, Inc. Memory cells and integrated structures

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1092952A (ja) * 1996-09-18 1998-04-10 Toshiba Corp 半導体記憶装置
JP2003243667A (ja) * 2002-02-22 2003-08-29 Toshiba Corp 半導体装置、半導体装置の製造方法、半導体基板の製造方法
US20060125010A1 (en) * 2003-02-10 2006-06-15 Arup Bhattacharyya Methods of forming transistor constructions
JP2006339309A (ja) * 2005-05-31 2006-12-14 Toshiba Corp 半導体装置とその製造方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5840855A (ja) * 1981-09-04 1983-03-09 Hitachi Ltd 半導体記憶素子
JPH06177375A (ja) * 1992-12-10 1994-06-24 Hitachi Ltd 半導体装置及びその製造方法
JP3361922B2 (ja) * 1994-09-13 2003-01-07 株式会社東芝 半導体装置
JP3407232B2 (ja) * 1995-02-08 2003-05-19 富士通株式会社 半導体記憶装置及びその動作方法
US5963817A (en) * 1997-10-16 1999-10-05 International Business Machines Corporation Bulk and strained silicon on insulator using local selective oxidation
KR100257765B1 (ko) * 1997-12-30 2000-06-01 김영환 기억소자 및 그 제조 방법
JP4713783B2 (ja) * 2000-08-17 2011-06-29 株式会社東芝 半導体メモリ装置
JP3884266B2 (ja) * 2001-02-19 2007-02-21 株式会社東芝 半導体メモリ装置及びその製造方法
JP2003031693A (ja) * 2001-07-19 2003-01-31 Toshiba Corp 半導体メモリ装置
KR20030034470A (ko) * 2001-10-23 2003-05-09 주식회사 하이닉스반도체 실리콘-게르마늄 채널을 포함하는 트랜지스터의 제조방법
JP4880867B2 (ja) * 2002-04-10 2012-02-22 セイコーインスツル株式会社 薄膜メモリ、アレイとその動作方法および製造方法
US7045401B2 (en) * 2003-06-23 2006-05-16 Sharp Laboratories Of America, Inc. Strained silicon finFET device
US6921982B2 (en) * 2003-07-21 2005-07-26 International Business Machines Corporation FET channel having a strained lattice structure along multiple surfaces
US20050062088A1 (en) * 2003-09-22 2005-03-24 Texas Instruments Incorporated Multi-gate one-transistor dynamic random access memory
US7057216B2 (en) 2003-10-31 2006-06-06 International Business Machines Corporation High mobility heterojunction complementary field effect transistors and methods thereof
US7244958B2 (en) 2004-06-24 2007-07-17 International Business Machines Corporation Integration of strained Ge into advanced CMOS technology
US7193279B2 (en) * 2005-01-18 2007-03-20 Intel Corporation Non-planar MOS structure with a strained channel region
US7517741B2 (en) * 2005-06-30 2009-04-14 Freescale Semiconductor, Inc. Single transistor memory cell with reduced recombination rates
US8410539B2 (en) 2006-02-14 2013-04-02 Stmicroelectronics (Crolles 2) Sas MOS transistor with a settable threshold
JP2008213624A (ja) 2007-03-02 2008-09-18 Toyota Motor Corp 操作機構および操作機構を備えた車両
US7928426B2 (en) * 2007-03-27 2011-04-19 Intel Corporation Forming a non-planar transistor having a quantum well channel
US7948008B2 (en) * 2007-10-26 2011-05-24 Micron Technology, Inc. Floating body field-effect transistors, and methods of forming floating body field-effect transistors
JP5403212B2 (ja) 2008-10-06 2014-01-29 株式会社Ｉｈｉ 白色ｌｅｄの製造装置と方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1092952A (ja) * 1996-09-18 1998-04-10 Toshiba Corp 半導体記憶装置
JP2003243667A (ja) * 2002-02-22 2003-08-29 Toshiba Corp 半導体装置、半導体装置の製造方法、半導体基板の製造方法
US20060125010A1 (en) * 2003-02-10 2006-06-15 Arup Bhattacharyya Methods of forming transistor constructions
JP2006339309A (ja) * 2005-05-31 2006-12-14 Toshiba Corp 半導体装置とその製造方法

Also Published As

Publication number Publication date
EP2284879A4 (en) 2012-05-23
EP2284879A2 (en) 2011-02-16
EP2284879B1 (en) 2020-05-06
KR20090114981A (ko) 2009-11-04
WO2009134089A3 (ko) 2010-02-11
TWI419327B (zh) 2013-12-11
WO2009134089A2 (ko) 2009-11-05
US20110127580A1 (en) 2011-06-02
JP2011519483A (ja) 2011-07-07
TW200950088A (en) 2009-12-01
US8860109B2 (en) 2014-10-14
JP5496184B2 (ja) 2014-05-21

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