JP5442224B2 - Ｓｏｉ基板の製造方法 - Google Patents

Ｓｏｉ基板の製造方法 Download PDF

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Publication number
JP5442224B2
JP5442224B2 JP2008184536A JP2008184536A JP5442224B2 JP 5442224 B2 JP5442224 B2 JP 5442224B2 JP 2008184536 A JP2008184536 A JP 2008184536A JP 2008184536 A JP2008184536 A JP 2008184536A JP 5442224 B2 JP5442224 B2 JP 5442224B2
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Prior art keywords
layer
substrate
semiconductor
semiconductor substrate
insulating layer
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Expired - Fee Related
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JP2008184536A
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Japanese (ja)
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JP2009049387A5 (https=
JP2009049387A (ja
Inventor
英人 大沼
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2008184536A priority Critical patent/JP5442224B2/ja
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Publication of JP2009049387A5 publication Critical patent/JP2009049387A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates

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  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Liquid Crystal (AREA)
  • Electroluminescent Light Sources (AREA)
JP2008184536A 2007-07-23 2008-07-16 Ｓｏｉ基板の製造方法 Expired - Fee Related JP5442224B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008184536A JP5442224B2 (ja) 2007-07-23 2008-07-16 Ｓｏｉ基板の製造方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007190987 2007-07-23
JP2007190987 2007-07-23
JP2008184536A JP5442224B2 (ja) 2007-07-23 2008-07-16 Ｓｏｉ基板の製造方法

Publications (3)

Publication Number Publication Date
JP2009049387A JP2009049387A (ja) 2009-03-05
JP2009049387A5 JP2009049387A5 (https=) 2011-07-14
JP5442224B2 true JP5442224B2 (ja) 2014-03-12

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Family Applications (1)

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JP2008184536A Expired - Fee Related JP5442224B2 (ja) 2007-07-23 2008-07-16 Ｓｏｉ基板の製造方法

Country Status (2)

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US (1) US8263476B2 (https=)
JP (1) JP5442224B2 (https=)

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JP5503876B2 (ja) * 2008-01-24 2014-05-28 株式会社半導体エネルギー研究所 半導体基板の製造方法
JP5552276B2 (ja) * 2008-08-01 2014-07-16 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
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JP5420968B2 (ja) 2009-05-07 2014-02-19 信越化学工業株式会社 貼り合わせウェーハの製造方法
JP2010278337A (ja) * 2009-05-29 2010-12-09 Shin-Etsu Chemical Co Ltd 表面欠陥密度が少ないｓｏｓ基板
JP2010278338A (ja) * 2009-05-29 2010-12-09 Shin-Etsu Chemical Co Ltd 界面近傍における欠陥密度が低いｓｏｓ基板
JP5643509B2 (ja) * 2009-12-28 2014-12-17 信越化学工業株式会社 応力を低減したｓｏｓ基板の製造方法
KR101243920B1 (ko) * 2010-01-07 2013-03-14 삼성디스플레이 주식회사 기판 밀봉에 사용되는 레이저 빔 조사 장치, 기판 밀봉 방법, 및 유기 발광 디스플레이 장치의 제조 방법
JP5279782B2 (ja) * 2010-09-16 2013-09-04 株式会社東芝 半導体装置の製造方法
TWI500118B (zh) 2010-11-12 2015-09-11 半導體能源研究所股份有限公司 半導體基底之製造方法
JP5695535B2 (ja) * 2011-09-27 2015-04-08 株式会社東芝 表示装置の製造方法
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WO2013187500A1 (ja) * 2012-06-15 2013-12-19 ランテクニカルサービス株式会社 電子素子の封止方法及び基板接合体
KR101803790B1 (ko) * 2013-04-18 2017-12-04 한화테크윈 주식회사 웨이퍼의 시닝 방법 및 장치
KR20140126439A (ko) * 2013-04-23 2014-10-31 삼성디스플레이 주식회사 투명 플렉시블 표시장치의 제조방법 및 이를 이용한 투명 플렉시블 표시장치
CN104252073B (zh) * 2013-06-27 2017-11-03 瀚宇彩晶股份有限公司 触控液晶显示器
JP5859497B2 (ja) * 2013-08-22 2016-02-10 信越化学工業株式会社 界面近傍における欠陥密度が低いｓｏｓ基板の製造方法
JP5859496B2 (ja) * 2013-08-22 2016-02-10 信越化学工業株式会社 表面欠陥密度が少ないｓｏｓ基板の製造方法
JP2015108735A (ja) * 2013-12-05 2015-06-11 旭硝子株式会社 電子デバイスの製造方法
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JP7001374B2 (ja) * 2017-06-19 2022-02-04 東京エレクトロン株式会社 成膜方法、記憶媒体及び成膜システム
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Publication number Publication date
US20090029525A1 (en) 2009-01-29
US8263476B2 (en) 2012-09-11
JP2009049387A (ja) 2009-03-05

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