JP5435720B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP5435720B2
JP5435720B2 JP2009289041A JP2009289041A JP5435720B2 JP 5435720 B2 JP5435720 B2 JP 5435720B2 JP 2009289041 A JP2009289041 A JP 2009289041A JP 2009289041 A JP2009289041 A JP 2009289041A JP 5435720 B2 JP5435720 B2 JP 5435720B2
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JP
Japan
Prior art keywords
gate electrode
region
semiconductor device
gate
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2009289041A
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English (en)
Japanese (ja)
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JP2011129811A5 (enExample
JP2011129811A (ja
Inventor
裕一 樋口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP2009289041A priority Critical patent/JP5435720B2/ja
Priority to PCT/JP2010/004887 priority patent/WO2011077606A1/ja
Publication of JP2011129811A publication Critical patent/JP2011129811A/ja
Publication of JP2011129811A5 publication Critical patent/JP2011129811A5/ja
Priority to US13/399,004 priority patent/US20120161245A1/en
Application granted granted Critical
Publication of JP5435720B2 publication Critical patent/JP5435720B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0128—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0147—Manufacturing their gate sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2009289041A 2009-12-21 2009-12-21 半導体装置 Expired - Fee Related JP5435720B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009289041A JP5435720B2 (ja) 2009-12-21 2009-12-21 半導体装置
PCT/JP2010/004887 WO2011077606A1 (ja) 2009-12-21 2010-08-03 半導体装置とその製造方法
US13/399,004 US20120161245A1 (en) 2009-12-21 2012-02-17 Semiconductor device and method for fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009289041A JP5435720B2 (ja) 2009-12-21 2009-12-21 半導体装置

Publications (3)

Publication Number Publication Date
JP2011129811A JP2011129811A (ja) 2011-06-30
JP2011129811A5 JP2011129811A5 (enExample) 2011-12-01
JP5435720B2 true JP5435720B2 (ja) 2014-03-05

Family

ID=44195160

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009289041A Expired - Fee Related JP5435720B2 (ja) 2009-12-21 2009-12-21 半導体装置

Country Status (3)

Country Link
US (1) US20120161245A1 (enExample)
JP (1) JP5435720B2 (enExample)
WO (1) WO2011077606A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5847537B2 (ja) * 2011-10-28 2016-01-27 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
US8822295B2 (en) 2012-04-03 2014-09-02 International Business Machines Corporation Low extension dose implants in SRAM fabrication
JP5927017B2 (ja) * 2012-04-20 2016-05-25 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
JP6275559B2 (ja) * 2014-06-13 2018-02-07 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
WO2017171881A1 (en) * 2016-04-01 2017-10-05 Intel Corporation Semiconductor device having sub regions to define threshold voltages

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3532625B2 (ja) * 1994-10-06 2004-05-31 東芝マイクロエレクトロニクス株式会社 半導体装置の製造方法
KR100214468B1 (ko) * 1995-12-29 1999-08-02 구본준 씨모스 소자 제조방법
JPH1167927A (ja) * 1997-06-09 1999-03-09 Mitsubishi Electric Corp 半導体装置およびその製造方法
KR19990030993A (ko) * 1997-10-08 1999-05-06 윤종용 고속동작을 위한 모스트랜지스터구조
US5989966A (en) * 1997-12-15 1999-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method and a deep sub-micron field effect transistor structure for suppressing short channel effects
US6124610A (en) * 1998-06-26 2000-09-26 Advanced Micro Devices, Inc. Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant
JP2000150885A (ja) * 1998-09-07 2000-05-30 Seiko Epson Corp Ｍｏｓトランジスタの閾値電圧設定方法および半導体装置
JP4481388B2 (ja) * 1999-06-25 2010-06-16 独立行政法人情報通信研究機構 絶縁ゲート型電界効果トランジスタおよびその製造方法
JP2001015704A (ja) 1999-06-29 2001-01-19 Hitachi Ltd 半導体集積回路
JP3275896B2 (ja) * 1999-10-06 2002-04-22 日本電気株式会社 半導体装置の製造方法
JP2001196475A (ja) * 2000-01-12 2001-07-19 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2002026139A (ja) * 2000-06-30 2002-01-25 Toshiba Corp 半導体装置及び半導体装置の製造方法
JP4635333B2 (ja) * 2000-12-14 2011-02-23 ソニー株式会社 半導体装置の製造方法
JP2002231821A (ja) * 2001-01-31 2002-08-16 Mitsubishi Electric Corp 半導体装置の製造方法及び半導体装置
JP2003197765A (ja) * 2001-12-28 2003-07-11 Texas Instr Japan Ltd 半導体装置およびその製造方法
US6849492B2 (en) * 2002-07-08 2005-02-01 Micron Technology, Inc. Method for forming standard voltage threshold and low voltage threshold MOSFET devices
JP2003249568A (ja) * 2003-01-31 2003-09-05 Oki Electric Ind Co Ltd 半導体装置の製造方法
JP4393109B2 (ja) * 2003-05-21 2010-01-06 株式会社ルネサステクノロジ 半導体装置の製造方法
US7064396B2 (en) * 2004-03-01 2006-06-20 Freescale Semiconductor, Inc. Integrated circuit with multiple spacer insulating region widths
JP2005303087A (ja) * 2004-04-13 2005-10-27 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
KR100827443B1 (ko) * 2006-10-11 2008-05-06 삼성전자주식회사 손상되지 않은 액티브 영역을 가진 반도체 소자 및 그 제조방법
US7456066B2 (en) * 2006-11-03 2008-11-25 Taiwan Semiconductor Manufacturing Co., Ltd. Variable width offset spacers for mixed signal and system on chip devices
JP4320405B2 (ja) * 2007-03-27 2009-08-26 Ｏｋｉセミコンダクタ株式会社 半導体装置及びその製造方法
US7718496B2 (en) * 2007-10-30 2010-05-18 International Business Machines Corporation Techniques for enabling multiple Vt devices using high-K metal gate stacks
JP2009141168A (ja) * 2007-12-07 2009-06-25 Panasonic Corp 半導体装置及びその製造方法
JP2009277771A (ja) * 2008-05-13 2009-11-26 Panasonic Corp 半導体装置とその製造方法
US7951678B2 (en) * 2008-08-12 2011-05-31 International Business Machines Corporation Metal-gate high-k reference structure
JP2010123669A (ja) * 2008-11-18 2010-06-03 Nec Electronics Corp 半導体装置およびその製造方法
JP2010153683A (ja) * 2008-12-26 2010-07-08 Hitachi Ltd 半導体装置
US8106455B2 (en) * 2009-04-30 2012-01-31 International Business Machines Corporation Threshold voltage adjustment through gate dielectric stack modification
DE102009021486B4 (de) * 2009-05-15 2013-07-04 Globalfoundries Dresden Module One Llc & Co. Kg Verfahren zur Feldeffekttransistor-Herstellung
US20100308418A1 (en) * 2009-06-09 2010-12-09 Knut Stahrenberg Semiconductor Devices and Methods of Manufacture Thereof
US8105892B2 (en) * 2009-08-18 2012-01-31 International Business Machines Corporation Thermal dual gate oxide device integration
US8283734B2 (en) * 2010-04-09 2012-10-09 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-threshold voltage device and method of making same
DE102010063781B4 (de) * 2010-12-21 2016-08-11 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Unterschiedliche Schwellwertspannungseinstellung in PMOS-Transistoren durch unterschiedliche Herstellung eines Kanalhalbleitermaterials

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Publication number Publication date
WO2011077606A1 (ja) 2011-06-30
JP2011129811A (ja) 2011-06-30
US20120161245A1 (en) 2012-06-28

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