JP5366797B2 - 絶縁層の上に厚さの異なる複数の半導体島を含む電子デバイスおよびその形成方法 - Google Patents

絶縁層の上に厚さの異なる複数の半導体島を含む電子デバイスおよびその形成方法 Download PDF

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JP5366797B2
JP5366797B2 JP2009500541A JP2009500541A JP5366797B2 JP 5366797 B2 JP5366797 B2 JP 5366797B2 JP 2009500541 A JP2009500541 A JP 2009500541A JP 2009500541 A JP2009500541 A JP 2009500541A JP 5366797 B2 JP5366797 B2 JP 5366797B2
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Japan
Prior art keywords
semiconductor
oxidation
layer
semiconductor island
resistant layer
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Expired - Fee Related
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JP2009500541A
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Japanese (ja)
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JP2009530828A5 (https=
JP2009530828A (ja
Inventor
ジー． サダカ、マリアム
ニュエン、ビチ−エン
テアン、ブン−ユー
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NXP USA Inc
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NXP USA Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/61—Formation of materials, e.g. in the shape of layers or pillars of insulating materials using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
    • H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
    • H10P14/6309—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors of silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6322—Formation by thermal treatments

Landscapes

  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2009500541A 2006-03-15 2007-02-22 絶縁層の上に厚さの異なる複数の半導体島を含む電子デバイスおよびその形成方法 Expired - Fee Related JP5366797B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/375,893 US7419866B2 (en) 2006-03-15 2006-03-15 Process of forming an electronic device including a semiconductor island over an insulating layer
US11/375,893 2006-03-15
PCT/US2007/062534 WO2007130728A2 (en) 2006-03-15 2007-02-22 Electronic device including semiconductor islands of different thicknesses over an insulating layer and a process of forming the same

Publications (3)

Publication Number Publication Date
JP2009530828A JP2009530828A (ja) 2009-08-27
JP2009530828A5 JP2009530828A5 (https=) 2010-03-11
JP5366797B2 true JP5366797B2 (ja) 2013-12-11

Family

ID=38518462

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009500541A Expired - Fee Related JP5366797B2 (ja) 2006-03-15 2007-02-22 絶縁層の上に厚さの異なる複数の半導体島を含む電子デバイスおよびその形成方法

Country Status (5)

Country Link
US (1) US7419866B2 (https=)
JP (1) JP5366797B2 (https=)
KR (1) KR20080102388A (https=)
TW (1) TWI390736B (https=)
WO (1) WO2007130728A2 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7456055B2 (en) 2006-03-15 2008-11-25 Freescale Semiconductor, Inc. Process for forming an electronic device including semiconductor fins
US8815712B2 (en) * 2011-12-28 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method for epitaxial re-growth of semiconductor region
US10366884B1 (en) * 2018-11-08 2019-07-30 Stratio Methods for forming a germanium island using selective epitaxial growth and a sacrificial filling layer

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3017860B2 (ja) * 1991-10-01 2000-03-13 株式会社東芝 半導体基体およびその製造方法とその半導体基体を用いた半導体装置
KR100218299B1 (ko) * 1996-02-05 1999-09-01 구본준 트랜지스터 제조방법
US6870225B2 (en) * 2001-11-02 2005-03-22 International Business Machines Corporation Transistor structure with thick recessed source/drain structures and fabrication process of same
JP2003332580A (ja) * 2002-05-09 2003-11-21 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US6720619B1 (en) * 2002-12-13 2004-04-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator chip incorporating partially-depleted, fully-depleted, and multiple-gate devices
US6867433B2 (en) * 2003-04-30 2005-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
US6909147B2 (en) * 2003-05-05 2005-06-21 International Business Machines Corporation Multi-height FinFETS
US6927146B2 (en) * 2003-06-17 2005-08-09 Intel Corporation Chemical thinning of epitaxial silicon layer over buried oxide
US6911383B2 (en) * 2003-06-26 2005-06-28 International Business Machines Corporation Hybrid planar and finFET CMOS devices
EP1519421A1 (en) 2003-09-25 2005-03-30 Interuniversitair Microelektronica Centrum Vzw Multiple gate semiconductor device and method for forming same
US7301206B2 (en) * 2003-08-01 2007-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors
US7075150B2 (en) * 2003-12-02 2006-07-11 International Business Machines Corporation Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique
US7247569B2 (en) * 2003-12-02 2007-07-24 International Business Machines Corporation Ultra-thin Si MOSFET device structure and method of manufacture
JP2005340768A (ja) * 2004-04-26 2005-12-08 Asahi Glass Co Ltd 多値不揮発性半導体記憶素子およびその製造方法
US20050275018A1 (en) * 2004-06-10 2005-12-15 Suresh Venkatesan Semiconductor device with multiple semiconductor layers
US7211474B2 (en) * 2005-01-18 2007-05-01 International Business Machines Corporation SOI device with body contact self-aligned to gate
US7432149B2 (en) * 2005-06-23 2008-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS on SOI substrates with hybrid crystal orientations

Also Published As

Publication number Publication date
WO2007130728A2 (en) 2007-11-15
KR20080102388A (ko) 2008-11-25
TW200742088A (en) 2007-11-01
US20070218707A1 (en) 2007-09-20
JP2009530828A (ja) 2009-08-27
US7419866B2 (en) 2008-09-02
TWI390736B (zh) 2013-03-21
WO2007130728A3 (en) 2008-11-06

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